Tue, 28 Dec 2010 17:23:04 +0000
fixes to Base RAM addressing -- 512K detected OK now, still need to deal with Expansion RAM detect issues
| src/memory.c | file | annotate | diff | revisions | |
| src/state.c | file | annotate | diff | revisions | |
| src/state.h | file | annotate | diff | revisions |
1.1 --- a/src/memory.c Tue Dec 28 16:59:40 2010 +0000 1.2 +++ b/src/memory.c Tue Dec 28 17:23:04 2010 +0000 1.3 @@ -235,7 +235,7 @@ 1.4 // This handles the "dummy DMA transfer" mentioned in the docs 1.5 // TODO: access check, peripheral access 1.6 if (!state.idmarw) 1.7 - WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD); 1.8 + WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD); 1.9 state.dma_count++; 1.10 handled = true; 1.11 break; 1.12 @@ -557,26 +557,31 @@ 1.13 1.14 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.15 // ROM access 1.16 - data = RD32(state.rom, address, ROM_SIZE - 1); 1.17 - } else if (address <= (state.ram_size - 1)) { 1.18 + return RD32(state.rom, address, ROM_SIZE - 1); 1.19 + } else if (address <= 0x3fffff) { 1.20 // RAM access 1.21 - data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1); 1.22 + uint32_t newAddr = mapAddr(address, false); 1.23 +// if (newAddr < state.base_ram_size) 1.24 + return RD32(state.base_ram, newAddr, state.base_ram_size - 1); 1.25 +// else 1.26 +// return 0xFFFFFFFF; 1.27 + // TODO: expansion RAM 1.28 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.29 // I/O register space, zone A 1.30 switch (address & 0x0F0000) { 1.31 case 0x000000: // Map RAM access 1.32 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address); 1.33 - data = RD32(state.map, address, 0x7FF); 1.34 + return RD32(state.map, address, 0x7FF); 1.35 break; 1.36 case 0x020000: // Video RAM 1.37 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address); 1.38 - data = RD32(state.vram, address, 0x7FFF); 1.39 + return RD32(state.vram, address, 0x7FFF); 1.40 break; 1.41 default: 1.42 - data = IoRead(address, 32); 1.43 + return IoRead(address, 32); 1.44 } 1.45 } else { 1.46 - data = IoRead(address, 32); 1.47 + return IoRead(address, 32); 1.48 } 1.49 1.50 return data; 1.51 @@ -599,9 +604,14 @@ 1.52 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.53 // ROM access 1.54 data = RD16(state.rom, address, ROM_SIZE - 1); 1.55 - } else if (address <= (state.ram_size - 1)) { 1.56 + } else if (address <= 0x3fffff) { 1.57 // RAM access 1.58 - data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1); 1.59 + uint32_t newAddr = mapAddr(address, false); 1.60 +// if (newAddr < state.base_ram_size) 1.61 + return RD16(state.base_ram, newAddr, state.base_ram_size - 1); 1.62 +// else 1.63 +// return 0xFFFFFFFF; 1.64 + // TODO: expansion RAM 1.65 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.66 // I/O register space, zone A 1.67 switch (address & 0x0F0000) { 1.68 @@ -640,9 +650,14 @@ 1.69 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.70 // ROM access 1.71 data = RD8(state.rom, address, ROM_SIZE - 1); 1.72 - } else if (address <= (state.ram_size - 1)) { 1.73 + } else if (address <= 0x3fffff) { 1.74 // RAM access 1.75 - data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1); 1.76 + uint32_t newAddr = mapAddr(address, false); 1.77 +// if (newAddr < state.base_ram_size) 1.78 + return RD8(state.base_ram, newAddr, state.base_ram_size - 1); 1.79 +// else 1.80 +// return 0xFFFFFFFF; 1.81 + // TODO: expansion RAM 1.82 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.83 // I/O register space, zone A 1.84 switch (address & 0x0F0000) { 1.85 @@ -678,9 +693,11 @@ 1.86 1.87 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.88 // ROM access 1.89 - } else if (address <= (state.ram_size - 1)) { 1.90 + } else if (address <= 0x3FFFFF) { 1.91 // RAM access 1.92 - WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value); 1.93 + uint32_t newAddr = mapAddr(address, true); 1.94 + if (newAddr <= 0x1fffff) //(state.base_ram_size - 1)) 1.95 + WR32(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.96 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.97 // I/O register space, zone A 1.98 switch (address & 0x0F0000) { 1.99 @@ -714,9 +731,11 @@ 1.100 1.101 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.102 // ROM access 1.103 - } else if (address <= (state.ram_size - 1)) { 1.104 + } else if (address <= 0x3FFFFF) { 1.105 // RAM access 1.106 - WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value); 1.107 + uint32_t newAddr = mapAddr(address, true); 1.108 + if (newAddr <= 0x1fffff) //(state.base_ram_size - 1)) 1.109 + WR16(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.110 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.111 // I/O register space, zone A 1.112 switch (address & 0x0F0000) { 1.113 @@ -750,9 +769,11 @@ 1.114 1.115 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.116 // ROM access (read only!) 1.117 - } else if (address <= (state.ram_size - 1)) { 1.118 + } else if (address <= 0x3FFFFF) { 1.119 // RAM access 1.120 - WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value); 1.121 + uint32_t newAddr = mapAddr(address, true); 1.122 + if (newAddr <= 0x1fffff) //(state.base_ram_size - 1)) 1.123 + WR8(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.124 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.125 // I/O register space, zone A 1.126 switch (address & 0x0F0000) {
2.1 --- a/src/state.c Tue Dec 28 16:59:40 2010 +0000 2.2 +++ b/src/state.c Tue Dec 28 17:23:04 2010 +0000 2.3 @@ -8,8 +8,8 @@ 2.4 int state_init(size_t ramsize) 2.5 { 2.6 // Free RAM if it's allocated 2.7 - if (state.ram != NULL) 2.8 - free(state.ram); 2.9 + if (state.base_ram != NULL) 2.10 + free(state.base_ram); 2.11 2.12 // Initialise hardware registers 2.13 state.romlmap = false; 2.14 @@ -18,10 +18,10 @@ 2.15 // Basically: 512KiB minimum, 4MiB maximum, in increments of 512KiB. 2.16 if ((ramsize < 512*1024) || ((ramsize % (512*1024)) != 0)) 2.17 return -1; 2.18 - state.ram = malloc(ramsize); 2.19 - if (state.ram == NULL) 2.20 + state.base_ram = malloc(ramsize); 2.21 + if (state.base_ram == NULL) 2.22 return -2; 2.23 - state.ram_size = ramsize; 2.24 + state.base_ram_size = ramsize; 2.25 2.26 // Load ROMs 2.27 FILE *r14c, *r15c; 2.28 @@ -81,9 +81,9 @@ 2.29 2.30 void state_done() 2.31 { 2.32 - if (state.ram != NULL) { 2.33 - free(state.ram); 2.34 - state.ram = NULL; 2.35 + if (state.base_ram != NULL) { 2.36 + free(state.base_ram); 2.37 + state.base_ram = NULL; 2.38 } 2.39 2.40 // Deinitialise the disc controller
3.1 --- a/src/state.h Tue Dec 28 16:59:40 2010 +0000 3.2 +++ b/src/state.h Tue Dec 28 17:23:04 2010 +0000 3.3 @@ -29,8 +29,8 @@ 3.4 uint8_t rom[ROM_SIZE]; ///< Boot PROM data buffer 3.5 3.6 //// Main system RAM 3.7 - uint8_t *ram; ///< RAM data buffer 3.8 - size_t ram_size; ///< Size of RAM buffer in bytes 3.9 + uint8_t *base_ram; ///< Base RAM data buffer 3.10 + size_t base_ram_size; ///< Size of Base RAM buffer in bytes 3.11 3.12 /// Video RAM 3.13 uint8_t vram[0x8000];