merge heads (properly this time)

Wed, 29 Dec 2010 09:04:43 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Wed, 29 Dec 2010 09:04:43 +0000
changeset 78
c149c13aff1c
parent 74
51cbc7a44cd9
parent 76
2ef98ea1e944
child 79
674226015c8a

merge heads (properly this time)

src/main.c file | annotate | diff | revisions
src/memory.c file | annotate | diff | revisions
src/state.c file | annotate | diff | revisions
src/wd279x.c file | annotate | diff | revisions
     1.1 --- a/src/main.c	Wed Dec 29 01:38:54 2010 +0000
     1.2 +++ b/src/main.c	Wed Dec 29 09:04:43 2010 +0000
     1.3 @@ -204,12 +204,13 @@
     1.4  	 * The 3B1 CPU runs at 10MHz, with DMA running at 1MHz and video refreshing at
     1.5  	 * around 60Hz (???), with a 60Hz periodic interrupt.
     1.6  	 */
     1.7 -	const uint32_t TIMESLOT_FREQUENCY = 240;	// Hz
     1.8 +	const uint32_t TIMESLOT_FREQUENCY = 1000;//240;	// Hz
     1.9  	const uint32_t MILLISECS_PER_TIMESLOT = 1e3 / TIMESLOT_FREQUENCY;
    1.10  	const uint32_t CLOCKS_PER_60HZ = (10e6 / 60);
    1.11  	uint32_t next_timeslot = SDL_GetTicks() + MILLISECS_PER_TIMESLOT;
    1.12  	uint32_t clock_cycles = 0;
    1.13  	bool exitEmu = false;
    1.14 +	bool lastirq_fdc = false;
    1.15  	for (;;) {
    1.16  		// Run the CPU for however many cycles we need to. CPU core clock is
    1.17  		// 10MHz, and we're running at 240Hz/timeslot. Thus: 10e6/240 or
    1.18 @@ -217,8 +218,7 @@
    1.19  		clock_cycles += m68k_execute(10e6/TIMESLOT_FREQUENCY);
    1.20  
    1.21  		// Run the DMA engine
    1.22 -		//
    1.23 -		if (state.dmaen) { //((state.dma_count < 0x3fff) && state.dmaen) {
    1.24 +		if (state.dmaen) {
    1.25  			// DMA ready to go -- so do it.
    1.26  			size_t num = 0;
    1.27  			while (state.dma_count < 0x4000) {
    1.28 @@ -325,8 +325,13 @@
    1.29  		}
    1.30  
    1.31  		// Any interrupts? --> TODO: masking
    1.32 -/*		if (wd2797_get_irq(&state.fdc_ctx)) {
    1.33 -			m68k_set_irq(2);
    1.34 +/*		if (!lastirq_fdc) {
    1.35 +			if (wd2797_get_irq(&state.fdc_ctx)) {
    1.36 +				lastirq_fdc = true;
    1.37 +				m68k_set_irq(2);
    1.38 +			} else {
    1.39 +				lastirq_fdc = false;
    1.40 +			}
    1.41  		} else {
    1.42  			m68k_set_irq(0);
    1.43  		}
     2.1 --- a/src/memory.c	Wed Dec 29 01:38:54 2010 +0000
     2.2 +++ b/src/memory.c	Wed Dec 29 09:04:43 2010 +0000
     2.3 @@ -438,7 +438,7 @@
     2.4  				break;
     2.5  			case 0x070000:				// Line Printer Status Register
     2.6  				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
     2.7 -				data |= (state.fdc_ctx.irql) ? 0x00080008 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
     2.8 +				data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
     2.9  				return data;
    2.10  				break;
    2.11  			case 0x080000:				// Real Time Clock
     3.1 --- a/src/state.c	Wed Dec 29 01:38:54 2010 +0000
     3.2 +++ b/src/state.c	Wed Dec 29 09:04:43 2010 +0000
     3.3 @@ -15,6 +15,12 @@
     3.4  
     3.5  	// Initialise hardware registers
     3.6  	state.romlmap = false;
     3.7 +	state.idmarw = state.dmaen = state.dmaenb = false;
     3.8 +	state.dma_count = state.dma_address = 0;
     3.9 +	state.pie = 0;
    3.10 +	state.leds = 0;
    3.11 +	state.genstat = 0;				// FIXME: check this
    3.12 +	state.bsr0 = state.bsr1 = 0;	// FIXME: check this
    3.13  
    3.14  	// Allocate Base RAM, making sure the user has specified a valid RAM amount first
    3.15  	// Basically: 512KiB minimum, 2MiB maximum, in increments of 512KiB.
     4.1 --- a/src/wd279x.c	Wed Dec 29 01:38:54 2010 +0000
     4.2 +++ b/src/wd279x.c	Wed Dec 29 09:04:43 2010 +0000
     4.3 @@ -37,19 +37,20 @@
     4.4  	ctx->track = ctx->head = ctx->sector = 0;
     4.5  
     4.6  	// no IRQ pending
     4.7 -	ctx->irql = ctx->irqe = false;
     4.8 +	ctx->irq = false;
     4.9  
    4.10  	// no data available
    4.11  	ctx->data_pos = ctx->data_len = 0;
    4.12  	ctx->data = NULL;
    4.13  
    4.14 -	// Status register clear, not busy
    4.15 +	// Status register clear, not busy; type1 command
    4.16  	ctx->status = 0;
    4.17 +	ctx->cmd_has_drq = false;
    4.18  
    4.19  	// Clear data register
    4.20  	ctx->data_reg = 0;
    4.21  
    4.22 -	// Last step direction
    4.23 +	// Last step direction = "towards zero"
    4.24  	ctx->last_step_dir = -1;
    4.25  
    4.26  	// No disc image loaded
    4.27 @@ -64,7 +65,7 @@
    4.28  	ctx->track = ctx->head = ctx->sector = 0;
    4.29  
    4.30  	// no IRQ pending
    4.31 -	ctx->irql = ctx->irqe = false;
    4.32 +	ctx->irq = false;
    4.33  
    4.34  	// no data available
    4.35  	ctx->data_pos = ctx->data_len = 0;
    4.36 @@ -95,13 +96,7 @@
    4.37  
    4.38  bool wd2797_get_irq(WD2797_CTX *ctx)
    4.39  {
    4.40 -	// If an IRQ is pending, clear it and return true, otherwise return false
    4.41 -	if (ctx->irqe) {
    4.42 -		ctx->irqe = false;
    4.43 -		return true;
    4.44 -	} else {
    4.45 -		return false;
    4.46 -	}
    4.47 +	return ctx->irq;
    4.48  }
    4.49  
    4.50  
    4.51 @@ -169,8 +164,7 @@
    4.52  	switch (addr & 0x03) {
    4.53  		case WD2797_REG_STATUS:		// Status register
    4.54  			// Read from status register clears IRQ
    4.55 -			ctx->irql = false;
    4.56 -			ctx->irqe = false;
    4.57 +			ctx->irq = false;
    4.58  
    4.59  			// Get current status flags (set by last command)
    4.60  			// DRQ bit
    4.61 @@ -197,9 +191,8 @@
    4.62  			if (ctx->data_pos < ctx->data_len) {
    4.63  				// set IRQ if this is the last data byte
    4.64  				if (ctx->data_pos == (ctx->data_len-1)) {
    4.65 -					// Set IRQ only if IRQL has been cleared (no pending IRQs)
    4.66 -					ctx->irqe = ctx->irql ? ctx->irqe : true;
    4.67 -					ctx->irql = true;
    4.68 +					// Set IRQ
    4.69 +					ctx->irq = true;
    4.70  				}
    4.71  				// return data byte and increment pointer
    4.72  				return ctx->data[ctx->data_pos++];
    4.73 @@ -228,7 +221,7 @@
    4.74  	switch (addr) {
    4.75  		case WD2797_REG_COMMAND:	// Command register
    4.76  			// write to command register clears interrupt request
    4.77 -			ctx->irql = false;
    4.78 +			ctx->irq = false;
    4.79  
    4.80  			// Is the drive ready?
    4.81  			if (ctx->disc_image == NULL) {
    4.82 @@ -319,9 +312,8 @@
    4.83  				// S0 = Busy. We just exec'd the command, thus we're not busy.
    4.84  				// 		TODO: Set a timer for seeks, and ONLY clear BUSY when that timer expires. Need periodics for that.
    4.85  				
    4.86 -				// Set IRQ only if IRQL has been cleared (no pending IRQs)
    4.87 -				ctx->irqe = ctx->irql ? ctx->irqe : true;
    4.88 -				ctx->irql = true;
    4.89 +				// Set IRQ
    4.90 +				ctx->irq = true;
    4.91  				return;
    4.92  			}
    4.93  
    4.94 @@ -344,9 +336,8 @@
    4.95  					// Set Write Protect bit and bail.
    4.96  					ctx->status = 0x40;
    4.97  
    4.98 -					// Set IRQ only if IRQL has been cleared (no pending IRQs)
    4.99 -					ctx->irqe = ctx->irql ? ctx->irqe : true;
   4.100 -					ctx->irql = true;
   4.101 +					// Set IRQ
   4.102 +					ctx->irq = true;
   4.103  
   4.104  					return;
   4.105  				}
   4.106 @@ -398,9 +389,8 @@
   4.107  						// CHS parameters exceed limits
   4.108  						ctx->status = 0x10;		// Record Not Found
   4.109  						break;
   4.110 -						// Set IRQ only if IRQL has been cleared (no pending IRQs)
   4.111 -						ctx->irqe = ctx->irql ? ctx->irqe : true;
   4.112 -						ctx->irql = true;
   4.113 +						// Set IRQ
   4.114 +						ctx->irq = true;
   4.115  					}
   4.116  
   4.117  					// reset data pointers
   4.118 @@ -485,9 +475,8 @@
   4.119  					// TODO!
   4.120  					ctx->status = 0;
   4.121  					ctx->data_pos = ctx->data_len = 0;
   4.122 -					// Set IRQ only if IRQL has been cleared (no pending IRQs)
   4.123 -					ctx->irqe = ctx->irql ? ctx->irqe : true;
   4.124 -					ctx->irql = true;
   4.125 +					// Set IRQ
   4.126 +					ctx->irq = true;
   4.127  					break;
   4.128  			}
   4.129  			break;
   4.130 @@ -509,9 +498,8 @@
   4.131  			if (ctx->data_pos < ctx->data_len) {
   4.132  				// set IRQ if this is the last data byte
   4.133  				if (ctx->data_pos == (ctx->data_len-1)) {
   4.134 -					// Set IRQ only if IRQL has been cleared (no pending IRQs)
   4.135 -					ctx->irqe = ctx->irql ? ctx->irqe : true;
   4.136 -					ctx->irql = true;
   4.137 +					// Set IRQ
   4.138 +					ctx->irq = true;
   4.139  				}
   4.140  
   4.141  				// store data byte and increment pointer
     5.1 --- a/src/wd279x.h	Wed Dec 29 01:38:54 2010 +0000
     5.2 +++ b/src/wd279x.h	Wed Dec 29 09:04:43 2010 +0000
     5.3 @@ -27,11 +27,8 @@
     5.4  	int						track, head, sector;
     5.5  	// Geometry of current disc
     5.6  	int						geom_secsz, geom_spt, geom_heads, geom_tracks;
     5.7 -	// IRQ status, level and edge sensitive.
     5.8 -	// Edge sensitive is cleared when host polls the IRQ status.
     5.9 -	// Level sensitive is cleared when emulated CPU polls the status reg or writes a new cmnd.
    5.10 -	// No EDGE sensitive interrupts will be issued unless the LEVEL SENSITIVE IRQ is clear.
    5.11 -	bool					irql, irqe;
    5.12 +	// IRQ status
    5.13 +	bool					irq;
    5.14  	// Status of last command
    5.15  	uint8_t					status;
    5.16  	// Last command uses DRQ bit?