add Map RAM emulation

Wed, 01 Dec 2010 22:43:52 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Wed, 01 Dec 2010 22:43:52 +0000
changeset 27
ceae676021ca
parent 26
fef12817c5e8
child 28
70665b05cb10

add Map RAM emulation

The emulator is now capable of booting up to the point where the BootPROM accesses the floppy and hard drive controllers.

Still TODO:
Lots of I/O registers
Memory mapping, banking and protection
Supervisor R/W restrictions (only SV mode code should be able to R/W I/O regs, user RAM is fair game)

src/main.c file | annotate | diff | revisions
     1.1 --- a/src/main.c	Wed Dec 01 22:34:15 2010 +0000
     1.2 +++ b/src/main.c	Wed Dec 01 22:43:52 2010 +0000
     1.3 @@ -62,7 +62,6 @@
     1.4   * m68k memory read/write support functions for Musashi
     1.5   ********************************************************/
     1.6  
     1.7 -
     1.8  // read m68k memory
     1.9  uint32_t m68k_read_memory_32(uint32_t address)
    1.10  {
    1.11 @@ -76,11 +75,14 @@
    1.12  		// ROM access
    1.13  		data = RD32(state.rom, address, ROM_SIZE - 1);
    1.14  	} else if (address <= (state.ram_size - 1)) {
    1.15 -		// RAM
    1.16 +		// RAM access -- TODO: mapping
    1.17  		data = RD32(state.ram, address, state.ram_size - 1);
    1.18  	} else if ((address >= 0x420000) && (address <= 0x427FFF)) {
    1.19 -		// VRAM
    1.20 +		// VRAM access
    1.21  		data = RD32(state.vram, address, 0x7FFF);
    1.22 +	} else if ((address >= 0x400000) && (address <= 0x4007FF)) {
    1.23 +		// Map RAM access
    1.24 +		data = RD32(state.map, address, 0x7FF);
    1.25  	} else {
    1.26  		// I/O register -- TODO
    1.27  		printf("RD32 0x%08X [unknown I/O register]\n", address);
    1.28 @@ -100,11 +102,14 @@
    1.29  		// ROM access
    1.30  		data = RD16(state.rom, address, ROM_SIZE - 1);
    1.31  	} else if (address <= (state.ram_size - 1)) {
    1.32 -		// RAM
    1.33 +		// RAM access -- TODO: mapping
    1.34  		data = RD16(state.ram, address, state.ram_size - 1);
    1.35  	} else if ((address >= 0x420000) && (address <= 0x427FFF)) {
    1.36 -		// VRAM
    1.37 +		// VRAM access
    1.38  		data = RD16(state.vram, address, 0x7FFF);
    1.39 +	} else if ((address >= 0x400000) && (address <= 0x4007FF)) {
    1.40 +		// Map RAM access
    1.41 +		data = RD16(state.map, address, 0x7FF);
    1.42  	} else {
    1.43  		// I/O register -- TODO
    1.44  		printf("RD16 0x%08X [unknown I/O register]\n", address);
    1.45 @@ -125,11 +130,14 @@
    1.46  		// ROM access
    1.47  		data = RD8(state.rom, address, ROM_SIZE - 1);
    1.48  	} else if (address <= (state.ram_size - 1)) {
    1.49 -		// RAM
    1.50 +		// RAM access -- TODO: mapping
    1.51  		data = RD8(state.ram, address, state.ram_size - 1);
    1.52  	} else if ((address >= 0x420000) && (address <= 0x427FFF)) {
    1.53 -		// VRAM
    1.54 +		// VRAM access
    1.55  		data = RD8(state.vram, address, 0x7FFF);
    1.56 +	} else if ((address >= 0x400000) && (address <= 0x4007FF)) {
    1.57 +		// Map RAM access
    1.58 +		data = RD8(state.map, address, 0x7FF);
    1.59  	} else {
    1.60  		// I/O register -- TODO
    1.61  		printf("RD08 0x%08X [unknown I/O register]\n", address);
    1.62 @@ -149,11 +157,14 @@
    1.63  		// ROM access
    1.64  		// TODO: bus error here? can't write to rom!
    1.65  	} else if (address <= (state.ram_size - 1)) {
    1.66 -		// RAM access
    1.67 +		// RAM -- TODO: mapping
    1.68  		WR32(state.ram, address, state.ram_size - 1, value);
    1.69  	} else if ((address >= 0x420000) && (address <= 0x427FFF)) {
    1.70  		// VRAM access
    1.71  		WR32(state.vram, address, 0x7fff, value);
    1.72 +	} else if ((address >= 0x400000) && (address <= 0x4007FF)) {
    1.73 +		// Map RAM access
    1.74 +		WR32(state.map, address, 0x7FF, value);
    1.75  	} else {
    1.76  		switch (address) {
    1.77  			case 0xE43000:	state.romlmap = ((value & 0x8000) == 0x8000); break;	// GCR3: ROMLMAP
    1.78 @@ -172,11 +183,14 @@
    1.79  		// ROM access
    1.80  		// TODO: bus error here? can't write to rom!
    1.81  	} else if (address <= (state.ram_size - 1)) {
    1.82 -		// RAM access
    1.83 +		// RAM access -- TODO: mapping
    1.84  		WR16(state.ram, address, state.ram_size - 1, value);
    1.85  	} else if ((address >= 0x420000) && (address <= 0x427FFF)) {
    1.86  		// VRAM access
    1.87  		WR16(state.vram, address, 0x7fff, value);
    1.88 +	} else if ((address >= 0x400000) && (address <= 0x4007FF)) {
    1.89 +		// Map RAM access
    1.90 +		WR16(state.map, address, 0x7FF, value);
    1.91  	} else {
    1.92  		switch (address) {
    1.93  			case 0xE43000:	state.romlmap = ((value & 0x8000) == 0x8000); break;	// GCR3: ROMLMAP
    1.94 @@ -203,11 +217,14 @@
    1.95  		// ROM access
    1.96  		// TODO: bus error here? can't write to rom!
    1.97  	} else if (address <= (state.ram_size - 1)) {
    1.98 -		// RAM access
    1.99 +		// RAM access -- TODO: mapping
   1.100  		WR8(state.ram, address, state.ram_size - 1, value);
   1.101  	} else if ((address >= 0x420000) && (address <= 0x427FFF)) {
   1.102  		// VRAM access
   1.103  		WR8(state.vram, address, 0x7fff, value);
   1.104 +	} else if ((address >= 0x400000) && (address <= 0x4007FF)) {
   1.105 +		// Map RAM access
   1.106 +		WR8(state.map, address, 0x7FF, value);
   1.107  	} else {
   1.108  		switch (address) {
   1.109  			case 0xE43000:	state.romlmap = ((value & 0x80) == 0x80); break;	// GCR3: ROMLMAP
   1.110 @@ -221,6 +238,11 @@
   1.111  uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
   1.112  uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
   1.113  
   1.114 +
   1.115 +/****************************
   1.116 + * blessed be thy main()...
   1.117 + ****************************/
   1.118 +
   1.119  int main(void)
   1.120  {
   1.121  	// copyright banner