Wed, 01 Dec 2010 22:34:15 +0000
move repeated R/W bit-shifting stuff into macros and fix RAM addressing issue
| src/main.c | file | annotate | diff | revisions | |
| src/state.h | file | annotate | diff | revisions |
1.1 --- a/src/main.c Wed Dec 01 22:15:41 2010 +0000 1.2 +++ b/src/main.c Wed Dec 01 22:34:15 2010 +0000 1.3 @@ -18,6 +18,51 @@ 1.4 exit(EXIT_FAILURE); 1.5 } 1.6 1.7 +/*********************************** 1.8 + * Array read/write utility macros 1.9 + * "Don't Repeat Yourself" :) 1.10 + ***********************************/ 1.11 + 1.12 +/// Array read, 32-bit 1.13 +#define RD32(array, address, andmask) \ 1.14 + (((uint32_t)array[(address + 0) & (andmask)] << 24) | \ 1.15 + ((uint32_t)array[(address + 1) & (andmask)] << 16) | \ 1.16 + ((uint32_t)array[(address + 2) & (andmask)] << 8) | \ 1.17 + ((uint32_t)array[(address + 3) & (andmask)])) 1.18 + 1.19 +/// Array read, 16-bit 1.20 +#define RD16(array, address, andmask) \ 1.21 + (((uint32_t)array[(address + 0) & (andmask)] << 8) | \ 1.22 + ((uint32_t)array[(address + 1) & (andmask)])) 1.23 + 1.24 +/// Array read, 8-bit 1.25 +#define RD8(array, address, andmask) \ 1.26 + ((uint32_t)array[(address + 0) & (andmask)]) 1.27 + 1.28 +/// Array write, 32-bit 1.29 +#define WR32(array, address, andmask, value) { \ 1.30 + array[(address + 0) & (andmask)] = (value >> 24) & 0xff; \ 1.31 + array[(address + 1) & (andmask)] = (value >> 16) & 0xff; \ 1.32 + array[(address + 2) & (andmask)] = (value >> 8) & 0xff; \ 1.33 + array[(address + 3) & (andmask)] = value & 0xff; \ 1.34 +} 1.35 + 1.36 +/// Array write, 16-bit 1.37 +#define WR16(array, address, andmask, value) { \ 1.38 + array[(address + 0) & (andmask)] = (value >> 8) & 0xff; \ 1.39 + array[(address + 1) & (andmask)] = value & 0xff; \ 1.40 +} 1.41 + 1.42 +/// Array write, 8-bit 1.43 +#define WR8(array, address, andmask, value) \ 1.44 + array[(address + 0) & (andmask)] = value & 0xff; 1.45 + 1.46 + 1.47 +/******************************************************** 1.48 + * m68k memory read/write support functions for Musashi 1.49 + ********************************************************/ 1.50 + 1.51 + 1.52 // read m68k memory 1.53 uint32_t m68k_read_memory_32(uint32_t address) 1.54 { 1.55 @@ -29,22 +74,13 @@ 1.56 1.57 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.58 // ROM access 1.59 - data = (((uint32_t)state.rom[(address + 0) & (ROM_SIZE - 1)] << 24) | 1.60 - ((uint32_t)state.rom[(address + 1) & (ROM_SIZE - 1)] << 16) | 1.61 - ((uint32_t)state.rom[(address + 2) & (ROM_SIZE - 1)] << 8) | 1.62 - ((uint32_t)state.rom[(address + 3) & (ROM_SIZE - 1)])); 1.63 - } else if (address < state.ram_size - 1) { 1.64 + data = RD32(state.rom, address, ROM_SIZE - 1); 1.65 + } else if (address <= (state.ram_size - 1)) { 1.66 // RAM 1.67 - data = (((uint32_t)state.ram[address + 0] << 24) | 1.68 - ((uint32_t)state.ram[address + 1] << 16) | 1.69 - ((uint32_t)state.ram[address + 2] << 8) | 1.70 - ((uint32_t)state.ram[address + 3])); 1.71 + data = RD32(state.ram, address, state.ram_size - 1); 1.72 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.73 // VRAM 1.74 - data = (((uint32_t)state.vram[(address + 0) & 0x7fff] << 24) | 1.75 - ((uint32_t)state.vram[(address + 1) & 0x7fff] << 16) | 1.76 - ((uint32_t)state.vram[(address + 2) & 0x7fff] << 8) | 1.77 - ((uint32_t)state.vram[(address + 3) & 0x7fff])); 1.78 + data = RD32(state.vram, address, 0x7FFF); 1.79 } else { 1.80 // I/O register -- TODO 1.81 printf("RD32 0x%08X [unknown I/O register]\n", address); 1.82 @@ -62,16 +98,13 @@ 1.83 1.84 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.85 // ROM access 1.86 - data = ((state.rom[(address + 0) & (ROM_SIZE - 1)] << 8) | 1.87 - (state.rom[(address + 1) & (ROM_SIZE - 1)])); 1.88 - } else if (address < state.ram_size - 1) { 1.89 + data = RD16(state.rom, address, ROM_SIZE - 1); 1.90 + } else if (address <= (state.ram_size - 1)) { 1.91 // RAM 1.92 - data = ((state.ram[address + 0] << 8) | 1.93 - (state.ram[address + 1])); 1.94 + data = RD16(state.ram, address, state.ram_size - 1); 1.95 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.96 // VRAM 1.97 - data = (((uint16_t)state.vram[(address + 0) & 0x7fff] << 8) | 1.98 - ((uint16_t)state.vram[(address + 1) & 0x7fff])); 1.99 + data = RD16(state.vram, address, 0x7FFF); 1.100 } else { 1.101 // I/O register -- TODO 1.102 printf("RD16 0x%08X [unknown I/O register]\n", address); 1.103 @@ -90,13 +123,13 @@ 1.104 1.105 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.106 // ROM access 1.107 - data = state.rom[(address + 0) & (ROM_SIZE - 1)]; 1.108 - } else if (address < state.ram_size) { 1.109 - // RAM access 1.110 - data = state.ram[address + 0]; 1.111 + data = RD8(state.rom, address, ROM_SIZE - 1); 1.112 + } else if (address <= (state.ram_size - 1)) { 1.113 + // RAM 1.114 + data = RD8(state.ram, address, state.ram_size - 1); 1.115 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.116 // VRAM 1.117 - data = state.vram[(address + 0) & 0x7fff]; 1.118 + data = RD8(state.vram, address, 0x7FFF); 1.119 } else { 1.120 // I/O register -- TODO 1.121 printf("RD08 0x%08X [unknown I/O register]\n", address); 1.122 @@ -115,18 +148,12 @@ 1.123 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.124 // ROM access 1.125 // TODO: bus error here? can't write to rom! 1.126 - } else if (address < state.ram_size) { 1.127 + } else if (address <= (state.ram_size - 1)) { 1.128 // RAM access 1.129 - state.ram[address + 0] = (value >> 24) & 0xff; 1.130 - state.ram[address + 1] = (value >> 16) & 0xff; 1.131 - state.ram[address + 2] = (value >> 8) & 0xff; 1.132 - state.ram[address + 3] = value & 0xff; 1.133 + WR32(state.ram, address, state.ram_size - 1, value); 1.134 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.135 // VRAM access 1.136 - state.vram[(address + 0) & 0x7fff] = (value >> 24) & 0xff; 1.137 - state.vram[(address + 1) & 0x7fff] = (value >> 16) & 0xff; 1.138 - state.vram[(address + 2) & 0x7fff] = (value >> 8) & 0xff; 1.139 - state.vram[(address + 3) & 0x7fff] = value & 0xff; 1.140 + WR32(state.vram, address, 0x7fff, value); 1.141 } else { 1.142 switch (address) { 1.143 case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); break; // GCR3: ROMLMAP 1.144 @@ -144,14 +171,12 @@ 1.145 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.146 // ROM access 1.147 // TODO: bus error here? can't write to rom! 1.148 - } else if (address < state.ram_size) { 1.149 + } else if (address <= (state.ram_size - 1)) { 1.150 // RAM access 1.151 - state.ram[address + 0] = (value >> 8) & 0xff; 1.152 - state.ram[address + 1] = value & 0xff; 1.153 + WR16(state.ram, address, state.ram_size - 1, value); 1.154 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.155 // VRAM access 1.156 - state.vram[(address + 0) & 0x7fff] = (value >> 8) & 0xff; 1.157 - state.vram[(address + 1) & 0x7fff] = value & 0xff; 1.158 + WR16(state.vram, address, 0x7fff, value); 1.159 } else { 1.160 switch (address) { 1.161 case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); break; // GCR3: ROMLMAP 1.162 @@ -177,11 +202,12 @@ 1.163 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.164 // ROM access 1.165 // TODO: bus error here? can't write to rom! 1.166 - } else if (address < state.ram_size) { 1.167 - state.ram[address] = value & 0xff; 1.168 + } else if (address <= (state.ram_size - 1)) { 1.169 + // RAM access 1.170 + WR8(state.ram, address, state.ram_size - 1, value); 1.171 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.172 // VRAM access 1.173 - state.vram[address & 0x7fff] = value; 1.174 + WR8(state.vram, address, 0x7fff, value); 1.175 } else { 1.176 switch (address) { 1.177 case 0xE43000: state.romlmap = ((value & 0x80) == 0x80); break; // GCR3: ROMLMAP
2.1 --- a/src/state.h Wed Dec 01 22:15:41 2010 +0000 2.2 +++ b/src/state.h Wed Dec 01 22:34:15 2010 +0000 2.3 @@ -24,6 +24,9 @@ 2.4 // Video RAM 2.5 uint8_t vram[0x8000]; ///< Video RAM 2.6 2.7 + // Map RAM 2.8 + uint8_t map[0x800]; ///< Map RAM 2.9 + 2.10 // GENERAL CONTROL REGISTER 2.11 /// GENCON.ROMLMAP -- false ORs the address with 0x800000, forcing the 2.12 /// 68010 to access ROM instead of RAM when booting. TRM page 2-36.