jtag_cores.v

Sun, 06 Mar 2011 19:32:57 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 19:32:57 +0000
changeset 15
27f96ec74b85
parent 14
54dd95f89113
child 16
5fb37de64edc
permissions
-rwxr-xr-x

fix jtag_cores typo

Original-Author: lekernel
Original-Source: milkymist 96d0e3995ce0c9d7cbb7

philpem@14 1 // TODO
philpem@0 2
philpem@14 3 module jtag_cores (
philpem@0 4 // ----- Inputs -------
philpem@0 5 reg_d,
philpem@0 6 reg_addr_d,
philpem@0 7 // ----- Outputs -------
philpem@0 8 reg_update,
philpem@0 9 reg_q,
philpem@0 10 reg_addr_q,
philpem@0 11 jtck,
philpem@0 12 jrstn
philpem@14 13 );
philpem@0 14
philpem@0 15 input [7:0] reg_d;
philpem@0 16 input [2:0] reg_addr_d;
philpem@0 17
philpem@0 18 output reg_update;
philpem@0 19 wire reg_update;
philpem@0 20 output [7:0] reg_q;
philpem@0 21 wire [7:0] reg_q;
philpem@0 22 output [2:0] reg_addr_q;
philpem@0 23 wire [2:0] reg_addr_q;
philpem@0 24
philpem@0 25 output jtck;
philpem@14 26 wire jtck;
philpem@0 27 output jrstn;
philpem@14 28 wire jrstn;
philpem@0 29
philpem@14 30 assign reg_update = 1'b0;
philpem@14 31 assign reg_q = 8'hxx;
philpem@14 32 assign reg_addr_q = 3'bxxx;
philpem@14 33 assign jtck = 1'b0;
philpem@14 34 assign jrstn = 1'b1;
philpem@0 35
philpem@0 36 endmodule