lm32_monitor.v

Sun, 06 Mar 2011 21:14:43 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:14:43 +0000
changeset 22
35dc7ba83714
parent 8
07be9df9fee8
child 26
73de224304c1
permissions
-rwxr-xr-x

[UPSTREAM PULL] Update baseline to LatticeMico32 v3.6 from Diamond 1.1-lm32 distribution package (datestamp Nov 2010)

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : lm32_monitor.v
philpem@0 19 // Title : Debug monitor memory Wishbone interface
philpem@0 20 // Version : 6.1.17
philpem@0 21 // : Initial Release
philpem@0 22 // Version : 7.0SP2, 3.0
philpem@0 23 // : No Change
philpem@0 24 // Version : 3.3
philpem@0 25 // : Removed port mismatch in instantiation of module
philpem@0 26 // : lm32_monitor_ram.
philpem@0 27 // =============================================================================
philpem@0 28
philpem@0 29 `include "system_conf.v"
philpem@0 30 `include "lm32_include.v"
philpem@0 31
philpem@0 32 /////////////////////////////////////////////////////
philpem@0 33 // Module interface
philpem@0 34 /////////////////////////////////////////////////////
philpem@0 35
philpem@0 36 module lm32_monitor (
philpem@0 37 // ----- Inputs -------
philpem@0 38 clk_i,
philpem@0 39 rst_i,
philpem@0 40 MON_ADR_I,
philpem@0 41 MON_CYC_I,
philpem@0 42 MON_DAT_I,
philpem@0 43 MON_SEL_I,
philpem@0 44 MON_STB_I,
philpem@0 45 MON_WE_I,
philpem@0 46 // ----- Outputs -------
philpem@0 47 MON_ACK_O,
philpem@0 48 MON_RTY_O,
philpem@0 49 MON_DAT_O,
philpem@0 50 MON_ERR_O
philpem@0 51 );
philpem@0 52
philpem@0 53 /////////////////////////////////////////////////////
philpem@0 54 // Inputs
philpem@0 55 /////////////////////////////////////////////////////
philpem@0 56
philpem@0 57 input clk_i; // Wishbone clock
philpem@0 58 input rst_i; // Wishbone reset
philpem@8 59 input [10:2] MON_ADR_I; // Wishbone address
philpem@0 60 input MON_STB_I; // Wishbone strobe
philpem@0 61 input MON_CYC_I; // Wishbone cycle
philpem@0 62 input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data
philpem@0 63 input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select
philpem@0 64 input MON_WE_I; // Wishbone write enable
philpem@0 65
philpem@0 66 /////////////////////////////////////////////////////
philpem@0 67 // Outputs
philpem@0 68 /////////////////////////////////////////////////////
philpem@0 69
philpem@0 70 output MON_ACK_O; // Wishbone acknowlege
philpem@0 71 reg MON_ACK_O;
philpem@0 72 output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output
philpem@0 73 reg [`LM32_WORD_RNG] MON_DAT_O;
philpem@0 74 output MON_RTY_O; // Wishbone retry
philpem@0 75 wire MON_RTY_O;
philpem@0 76 output MON_ERR_O; // Wishbone error
philpem@0 77 wire MON_ERR_O;
philpem@0 78
philpem@0 79 /////////////////////////////////////////////////////
philpem@0 80 // Internal nets and registers
philpem@0 81 /////////////////////////////////////////////////////
philpem@0 82
philpem@0 83 reg [1:0] state; // Current state of FSM
philpem@0 84 wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM
philpem@0 85 reg write_enable; // RAM write enable
philpem@0 86 reg [`LM32_WORD_RNG] write_data; // RAM write data
philpem@0 87
philpem@0 88 /////////////////////////////////////////////////////
philpem@0 89 // Instantiations
philpem@0 90 /////////////////////////////////////////////////////
philpem@0 91
philpem@0 92 lm32_monitor_ram ram (
philpem@0 93 // ----- Inputs -------
philpem@0 94 .ClockA (clk_i),
philpem@0 95 .ClockB (clk_i),
philpem@0 96 .ResetA (rst_i),
philpem@0 97 .ResetB (rst_i),
philpem@0 98 .ClockEnA (`TRUE),
philpem@0 99 .ClockEnB (`FALSE),
philpem@0 100 .AddressA (MON_ADR_I[10:2]),
philpem@0 101 .AddressB (9'b0),
philpem@0 102 .DataInA (write_data),
philpem@0 103 .DataInB (32'b0),
philpem@0 104 .WrA (write_enable),
philpem@0 105 .WrB (`FALSE),
philpem@0 106 // ----- Outputs -------
philpem@0 107 .QA (data),
philpem@0 108 .QB (dataB)
philpem@0 109 );
philpem@0 110
philpem@0 111 /////////////////////////////////////////////////////
philpem@0 112 // Combinational Logic
philpem@0 113 /////////////////////////////////////////////////////
philpem@0 114
philpem@0 115 assign MON_RTY_O = `FALSE;
philpem@0 116 assign MON_ERR_O = `FALSE;
philpem@0 117
philpem@0 118 /////////////////////////////////////////////////////
philpem@0 119 // Sequential Logic
philpem@0 120 /////////////////////////////////////////////////////
philpem@0 121
philpem@0 122 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 123 begin
philpem@0 124 if (rst_i == `TRUE)
philpem@0 125 begin
philpem@0 126 write_enable <= `FALSE;
philpem@0 127 MON_ACK_O <= `FALSE;
philpem@0 128 MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
philpem@0 129 state <= 2'b00;
philpem@0 130 end
philpem@0 131 else
philpem@0 132 begin
philpem@22 133 casez (state)
philpem@0 134 2'b01:
philpem@0 135 begin
philpem@0 136 // Output read data to Wishbone
philpem@0 137 MON_ACK_O <= `TRUE;
philpem@0 138 MON_DAT_O <= data;
philpem@0 139 // Sub-word writes are performed using read-modify-write
philpem@0 140 // as the Lattice EBRs don't support byte enables
philpem@0 141 if (MON_WE_I == `TRUE)
philpem@0 142 write_enable <= `TRUE;
philpem@0 143 write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
philpem@0 144 write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
philpem@0 145 write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
philpem@0 146 write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
philpem@0 147 state <= 2'b10;
philpem@0 148 end
philpem@0 149 2'b10:
philpem@0 150 begin
philpem@0 151 // Wishbone access occurs in this cycle
philpem@0 152 write_enable <= `FALSE;
philpem@0 153 MON_ACK_O <= `FALSE;
philpem@0 154 MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
philpem@0 155 state <= 2'b00;
philpem@0 156 end
philpem@22 157 default:
philpem@22 158 begin
philpem@22 159 write_enable <= `FALSE;
philpem@22 160 MON_ACK_O <= `FALSE;
philpem@22 161 // Wait for a Wishbone access
philpem@22 162 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
philpem@22 163 state <= 2'b01;
philpem@22 164 end
philpem@0 165 endcase
philpem@0 166 end
philpem@0 167 end
philpem@0 168
philpem@0 169 endmodule