jtag_cores.v

Sun, 06 Mar 2011 19:49:17 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 19:49:17 +0000
changeset 17
50bf3061dbff
parent 16
5fb37de64edc
child 18
cc945f778cd7
permissions
-rwxr-xr-x

Enable Spartan 6 JTAG TAP only if selected (Michael Walle)

Original-Author: Michael Walle <michael walle.cc>
Original-Source: milkymist e7d77749236d73fcdc65

philpem@16 1 module jtag_cores (
philpem@16 2 input [7:0] reg_d,
philpem@16 3 input [2:0] reg_addr_d,
philpem@16 4 output reg_update,
philpem@16 5 output [7:0] reg_q,
philpem@16 6 output [2:0] reg_addr_q,
philpem@16 7 output jtck,
philpem@16 8 output jrstn
philpem@16 9 );
philpem@0 10
philpem@16 11 wire tck;
philpem@16 12 wire tdi;
philpem@16 13 wire tdo;
philpem@16 14 wire shift;
philpem@16 15 wire update;
philpem@16 16 wire reset;
philpem@16 17
philpem@16 18 jtag_tap jtag_tap (
philpem@16 19 .tck(tck),
philpem@16 20 .tdi(tdi),
philpem@16 21 .tdo(tdo),
philpem@16 22 .shift(shift),
philpem@16 23 .update(update),
philpem@16 24 .reset(reset)
philpem@14 25 );
philpem@0 26
philpem@16 27 reg [10:0] jtag_shift;
philpem@16 28 reg [10:0] jtag_latched;
philpem@0 29
philpem@16 30 always @(posedge tck or posedge reset)
philpem@16 31 begin
philpem@16 32 if(reset)
philpem@16 33 jtag_shift <= 11'b0;
philpem@16 34 else begin
philpem@16 35 if(shift)
philpem@16 36 jtag_shift <= {tdi, jtag_shift[10:1]};
philpem@16 37 else
philpem@16 38 jtag_shift <= {reg_d, reg_addr_d};
philpem@16 39 end
philpem@16 40 end
philpem@0 41
philpem@16 42 assign tdo = jtag_shift[0];
philpem@0 43
philpem@16 44 always @(posedge reg_update or posedge reset)
philpem@16 45 begin
philpem@16 46 if(reset)
philpem@16 47 jtag_latched <= 11'b0;
philpem@16 48 else
philpem@16 49 jtag_latched <= jtag_shift;
philpem@16 50 end
philpem@16 51
philpem@17 52 assign reg_update = update;
philpem@16 53 assign reg_q = jtag_latched[10:3];
philpem@16 54 assign reg_addr_q = jtag_latched[2:0];
philpem@16 55 assign jtck = tck;
philpem@16 56 assign jrstn = ~reset;
philpem@16 57
philpem@0 58 endmodule