Sun, 06 Mar 2011 19:48:34 +0000
Add JTAG interface for Xilinx Spartan 6 (Michael Walle)
Original-Source: Milkymist mailing list posting, 2010-09-23
Original-Message-Id: <201009232334.04219.michael@walle.cc>
Original-Author: Michael Walle <michael walle.cc>
philpem@16 | 1 | module jtag_cores ( |
philpem@16 | 2 | input [7:0] reg_d, |
philpem@16 | 3 | input [2:0] reg_addr_d, |
philpem@16 | 4 | output reg_update, |
philpem@16 | 5 | output [7:0] reg_q, |
philpem@16 | 6 | output [2:0] reg_addr_q, |
philpem@16 | 7 | output jtck, |
philpem@16 | 8 | output jrstn |
philpem@16 | 9 | ); |
philpem@0 | 10 | |
philpem@16 | 11 | wire sel; |
philpem@16 | 12 | wire tck; |
philpem@16 | 13 | wire tdi; |
philpem@16 | 14 | wire tdo; |
philpem@16 | 15 | wire shift; |
philpem@16 | 16 | wire update; |
philpem@16 | 17 | wire reset; |
philpem@16 | 18 | |
philpem@16 | 19 | jtag_tap jtag_tap ( |
philpem@16 | 20 | .sel(sel), |
philpem@16 | 21 | .tck(tck), |
philpem@16 | 22 | .tdi(tdi), |
philpem@16 | 23 | .tdo(tdo), |
philpem@16 | 24 | .shift(shift), |
philpem@16 | 25 | .update(update), |
philpem@16 | 26 | .reset(reset) |
philpem@14 | 27 | ); |
philpem@0 | 28 | |
philpem@16 | 29 | reg [10:0] jtag_shift; |
philpem@16 | 30 | reg [10:0] jtag_latched; |
philpem@0 | 31 | |
philpem@16 | 32 | always @(posedge tck or posedge reset) |
philpem@16 | 33 | begin |
philpem@16 | 34 | if(reset) |
philpem@16 | 35 | jtag_shift <= 11'b0; |
philpem@16 | 36 | else begin |
philpem@16 | 37 | if(shift) |
philpem@16 | 38 | jtag_shift <= {tdi, jtag_shift[10:1]}; |
philpem@16 | 39 | else |
philpem@16 | 40 | jtag_shift <= {reg_d, reg_addr_d}; |
philpem@16 | 41 | end |
philpem@16 | 42 | end |
philpem@0 | 43 | |
philpem@16 | 44 | assign tdo = jtag_shift[0]; |
philpem@0 | 45 | |
philpem@16 | 46 | always @(posedge reg_update or posedge reset) |
philpem@16 | 47 | begin |
philpem@16 | 48 | if(reset) |
philpem@16 | 49 | jtag_latched <= 11'b0; |
philpem@16 | 50 | else |
philpem@16 | 51 | jtag_latched <= jtag_shift; |
philpem@16 | 52 | end |
philpem@16 | 53 | |
philpem@16 | 54 | assign reg_update = update & sel; |
philpem@16 | 55 | assign reg_q = jtag_latched[10:3]; |
philpem@16 | 56 | assign reg_addr_q = jtag_latched[2:0]; |
philpem@16 | 57 | assign jtck = tck; |
philpem@16 | 58 | assign jrstn = ~reset; |
philpem@16 | 59 | |
philpem@0 | 60 | endmodule |