Sat, 06 Aug 2011 00:02:46 +0100
[UPSTREAM PULL] Update baseline to LatticeMico32 v3.8 from Diamond 1.3-lm32 distribution package (datestamp May 2011)
philpem@26 | 1 | // ================================================================== |
philpem@26 | 2 | // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< |
philpem@26 | 3 | // ------------------------------------------------------------------ |
philpem@26 | 4 | // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation |
philpem@26 | 5 | // ALL RIGHTS RESERVED |
philpem@26 | 6 | // ------------------------------------------------------------------ |
philpem@26 | 7 | // |
philpem@26 | 8 | // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. |
philpem@26 | 9 | // |
philpem@26 | 10 | // Permission: |
philpem@26 | 11 | // |
philpem@26 | 12 | // Lattice Semiconductor grants permission to use this code |
philpem@26 | 13 | // pursuant to the terms of the Lattice Semiconductor Corporation |
philpem@26 | 14 | // Open Source License Agreement. |
philpem@26 | 15 | // |
philpem@26 | 16 | // Disclaimer: |
philpem@0 | 17 | // |
philpem@26 | 18 | // Lattice Semiconductor provides no warranty regarding the use or |
philpem@26 | 19 | // functionality of this code. It is the user's responsibility to |
philpem@26 | 20 | // verify the user’s design for consistency and functionality through |
philpem@26 | 21 | // the use of formal verification methods. |
philpem@26 | 22 | // |
philpem@26 | 23 | // -------------------------------------------------------------------- |
philpem@26 | 24 | // |
philpem@26 | 25 | // Lattice Semiconductor Corporation |
philpem@26 | 26 | // 5555 NE Moore Court |
philpem@26 | 27 | // Hillsboro, OR 97214 |
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philpem@26 | 29 | // |
philpem@26 | 30 | // TEL: 1-800-Lattice (USA and Canada) |
philpem@26 | 31 | // 503-286-8001 (other locations) |
philpem@26 | 32 | // |
philpem@26 | 33 | // web: http://www.latticesemi.com/ |
philpem@26 | 34 | // email: techsupport@latticesemi.com |
philpem@26 | 35 | // |
philpem@26 | 36 | // -------------------------------------------------------------------- |
philpem@0 | 37 | // FILE DETAILS |
philpem@0 | 38 | // Project : LatticeMico32 |
philpem@0 | 39 | // File : lm32_jtag.v |
philpem@0 | 40 | // Title : JTAG interface |
philpem@0 | 41 | // Dependencies : lm32_include.v |
philpem@0 | 42 | // Version : 6.1.17 |
philpem@0 | 43 | // : Initial Release |
philpem@0 | 44 | // Version : 7.0SP2, 3.0 |
philpem@0 | 45 | // : No Change |
philpem@0 | 46 | // Version : 3.1 |
philpem@0 | 47 | // : No Change |
philpem@0 | 48 | // ============================================================================= |
philpem@0 | 49 | |
philpem@0 | 50 | `include "lm32_include.v" |
philpem@0 | 51 | |
philpem@0 | 52 | `ifdef CFG_JTAG_ENABLED |
philpem@0 | 53 | |
philpem@0 | 54 | `define LM32_DP 3'b000 |
philpem@0 | 55 | `define LM32_TX 3'b001 |
philpem@0 | 56 | `define LM32_RX 3'b010 |
philpem@0 | 57 | |
philpem@0 | 58 | // LM32 Debug Protocol commands IDs |
philpem@0 | 59 | `define LM32_DP_RNG 3:0 |
philpem@0 | 60 | `define LM32_DP_READ_MEMORY 4'b0001 |
philpem@0 | 61 | `define LM32_DP_WRITE_MEMORY 4'b0010 |
philpem@0 | 62 | `define LM32_DP_READ_SEQUENTIAL 4'b0011 |
philpem@0 | 63 | `define LM32_DP_WRITE_SEQUENTIAL 4'b0100 |
philpem@0 | 64 | `define LM32_DP_WRITE_CSR 4'b0101 |
philpem@0 | 65 | `define LM32_DP_BREAK 4'b0110 |
philpem@0 | 66 | `define LM32_DP_RESET 4'b0111 |
philpem@0 | 67 | |
philpem@0 | 68 | // States for FSM |
philpem@0 | 69 | `define LM32_JTAG_STATE_RNG 3:0 |
philpem@0 | 70 | `define LM32_JTAG_STATE_READ_COMMAND 4'h0 |
philpem@0 | 71 | `define LM32_JTAG_STATE_READ_BYTE_0 4'h1 |
philpem@0 | 72 | `define LM32_JTAG_STATE_READ_BYTE_1 4'h2 |
philpem@0 | 73 | `define LM32_JTAG_STATE_READ_BYTE_2 4'h3 |
philpem@0 | 74 | `define LM32_JTAG_STATE_READ_BYTE_3 4'h4 |
philpem@0 | 75 | `define LM32_JTAG_STATE_READ_BYTE_4 4'h5 |
philpem@0 | 76 | `define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6 |
philpem@0 | 77 | `define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7 |
philpem@0 | 78 | `define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8 |
philpem@0 | 79 | |
philpem@0 | 80 | ///////////////////////////////////////////////////// |
philpem@0 | 81 | // Module interface |
philpem@0 | 82 | ///////////////////////////////////////////////////// |
philpem@0 | 83 | |
philpem@0 | 84 | module lm32_jtag ( |
philpem@0 | 85 | // ----- Inputs ------- |
philpem@0 | 86 | clk_i, |
philpem@0 | 87 | rst_i, |
philpem@0 | 88 | jtag_clk, |
philpem@0 | 89 | jtag_update, |
philpem@0 | 90 | jtag_reg_q, |
philpem@0 | 91 | jtag_reg_addr_q, |
philpem@0 | 92 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 93 | csr, |
philpem@0 | 94 | csr_write_enable, |
philpem@0 | 95 | csr_write_data, |
philpem@0 | 96 | stall_x, |
philpem@0 | 97 | `endif |
philpem@0 | 98 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 99 | jtag_read_data, |
philpem@0 | 100 | jtag_access_complete, |
philpem@0 | 101 | `endif |
philpem@0 | 102 | `ifdef CFG_DEBUG_ENABLED |
philpem@0 | 103 | exception_q_w, |
philpem@0 | 104 | `endif |
philpem@0 | 105 | // ----- Outputs ------- |
philpem@0 | 106 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 107 | jtx_csr_read_data, |
philpem@0 | 108 | jrx_csr_read_data, |
philpem@0 | 109 | `endif |
philpem@0 | 110 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 111 | jtag_csr_write_enable, |
philpem@0 | 112 | jtag_csr_write_data, |
philpem@0 | 113 | jtag_csr, |
philpem@0 | 114 | jtag_read_enable, |
philpem@0 | 115 | jtag_write_enable, |
philpem@0 | 116 | jtag_write_data, |
philpem@0 | 117 | jtag_address, |
philpem@0 | 118 | `endif |
philpem@0 | 119 | `ifdef CFG_DEBUG_ENABLED |
philpem@0 | 120 | jtag_break, |
philpem@0 | 121 | jtag_reset, |
philpem@0 | 122 | `endif |
philpem@0 | 123 | jtag_reg_d, |
philpem@0 | 124 | jtag_reg_addr_d |
philpem@0 | 125 | ); |
philpem@0 | 126 | |
philpem@0 | 127 | parameter lat_family = `LATTICE_FAMILY; |
philpem@0 | 128 | |
philpem@0 | 129 | ///////////////////////////////////////////////////// |
philpem@0 | 130 | // Inputs |
philpem@0 | 131 | ///////////////////////////////////////////////////// |
philpem@0 | 132 | |
philpem@0 | 133 | input clk_i; // Clock |
philpem@0 | 134 | input rst_i; // Reset |
philpem@0 | 135 | |
philpem@0 | 136 | input jtag_clk; // JTAG clock |
philpem@0 | 137 | input jtag_update; // JTAG data register has been updated |
philpem@0 | 138 | input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register |
philpem@0 | 139 | input [2:0] jtag_reg_addr_q; // JTAG data register |
philpem@0 | 140 | |
philpem@0 | 141 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 142 | input [`LM32_CSR_RNG] csr; // CSR to write |
philpem@0 | 143 | input csr_write_enable; // CSR write enable |
philpem@0 | 144 | input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR |
philpem@0 | 145 | input stall_x; // Stall instruction in X stage |
philpem@0 | 146 | `endif |
philpem@0 | 147 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 148 | input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address |
philpem@0 | 149 | input jtag_access_complete; // Memory access if complete |
philpem@0 | 150 | `endif |
philpem@0 | 151 | `ifdef CFG_DEBUG_ENABLED |
philpem@0 | 152 | input exception_q_w; // Indicates an exception has occured in W stage |
philpem@0 | 153 | `endif |
philpem@0 | 154 | |
philpem@0 | 155 | ///////////////////////////////////////////////////// |
philpem@0 | 156 | // Outputs |
philpem@0 | 157 | ///////////////////////////////////////////////////// |
philpem@0 | 158 | |
philpem@0 | 159 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 160 | output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions |
philpem@0 | 161 | wire [`LM32_WORD_RNG] jtx_csr_read_data; |
philpem@0 | 162 | output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions |
philpem@0 | 163 | wire [`LM32_WORD_RNG] jrx_csr_read_data; |
philpem@0 | 164 | `endif |
philpem@0 | 165 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 166 | output jtag_csr_write_enable; // CSR write enable |
philpem@0 | 167 | reg jtag_csr_write_enable; |
philpem@0 | 168 | output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR |
philpem@0 | 169 | wire [`LM32_WORD_RNG] jtag_csr_write_data; |
philpem@0 | 170 | output [`LM32_CSR_RNG] jtag_csr; // CSR to write |
philpem@0 | 171 | wire [`LM32_CSR_RNG] jtag_csr; |
philpem@0 | 172 | output jtag_read_enable; // Memory read enable |
philpem@0 | 173 | reg jtag_read_enable; |
philpem@0 | 174 | output jtag_write_enable; // Memory write enable |
philpem@0 | 175 | reg jtag_write_enable; |
philpem@0 | 176 | output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address |
philpem@0 | 177 | wire [`LM32_BYTE_RNG] jtag_write_data; |
philpem@0 | 178 | output [`LM32_WORD_RNG] jtag_address; // Memory read/write address |
philpem@0 | 179 | wire [`LM32_WORD_RNG] jtag_address; |
philpem@0 | 180 | `endif |
philpem@0 | 181 | `ifdef CFG_DEBUG_ENABLED |
philpem@0 | 182 | output jtag_break; // Request to raise a breakpoint exception |
philpem@0 | 183 | reg jtag_break; |
philpem@0 | 184 | output jtag_reset; // Request to raise a reset exception |
philpem@0 | 185 | reg jtag_reset; |
philpem@0 | 186 | `endif |
philpem@0 | 187 | output [`LM32_BYTE_RNG] jtag_reg_d; |
philpem@0 | 188 | reg [`LM32_BYTE_RNG] jtag_reg_d; |
philpem@0 | 189 | output [2:0] jtag_reg_addr_d; |
philpem@0 | 190 | wire [2:0] jtag_reg_addr_d; |
philpem@0 | 191 | |
philpem@0 | 192 | ///////////////////////////////////////////////////// |
philpem@0 | 193 | // Internal nets and registers |
philpem@0 | 194 | ///////////////////////////////////////////////////// |
philpem@0 | 195 | |
philpem@0 | 196 | reg rx_toggle; // Clock-domain crossing registers |
philpem@0 | 197 | reg rx_toggle_r; // Registered version of rx_toggle |
philpem@0 | 198 | reg rx_toggle_r_r; // Registered version of rx_toggle_r |
philpem@0 | 199 | reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r |
philpem@0 | 200 | |
philpem@0 | 201 | reg [`LM32_BYTE_RNG] rx_byte; |
philpem@0 | 202 | reg [2:0] rx_addr; |
philpem@0 | 203 | |
philpem@0 | 204 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 205 | reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data |
philpem@0 | 206 | reg uart_tx_valid; // TX data is valid |
philpem@0 | 207 | reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data |
philpem@0 | 208 | reg uart_rx_valid; // RX data is valid |
philpem@0 | 209 | `endif |
philpem@0 | 210 | |
philpem@0 | 211 | reg [`LM32_DP_RNG] command; // The last received command |
philpem@0 | 212 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 213 | reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters |
philpem@0 | 214 | reg [`LM32_BYTE_RNG] jtag_byte_1; |
philpem@0 | 215 | reg [`LM32_BYTE_RNG] jtag_byte_2; |
philpem@0 | 216 | reg [`LM32_BYTE_RNG] jtag_byte_3; |
philpem@0 | 217 | reg [`LM32_BYTE_RNG] jtag_byte_4; |
philpem@0 | 218 | reg processing; // Indicates if we're still processing a memory read/write |
philpem@0 | 219 | `endif |
philpem@0 | 220 | |
philpem@0 | 221 | reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM |
philpem@0 | 222 | |
philpem@0 | 223 | ///////////////////////////////////////////////////// |
philpem@0 | 224 | // Combinational Logic |
philpem@0 | 225 | ///////////////////////////////////////////////////// |
philpem@0 | 226 | |
philpem@0 | 227 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 228 | assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; |
philpem@0 | 229 | assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG]; |
philpem@0 | 230 | assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; |
philpem@0 | 231 | assign jtag_write_data = jtag_byte_4; |
philpem@0 | 232 | `endif |
philpem@0 | 233 | |
philpem@0 | 234 | // Generate status flags for reading via the JTAG interface |
philpem@0 | 235 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 236 | assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; |
philpem@0 | 237 | `else |
philpem@0 | 238 | assign jtag_reg_addr_d[1:0] = 2'b00; |
philpem@0 | 239 | `endif |
philpem@0 | 240 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 241 | assign jtag_reg_addr_d[2] = processing; |
philpem@0 | 242 | `else |
philpem@0 | 243 | assign jtag_reg_addr_d[2] = 1'b0; |
philpem@0 | 244 | `endif |
philpem@0 | 245 | |
philpem@0 | 246 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 247 | assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00}; |
philpem@0 | 248 | assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte}; |
philpem@0 | 249 | `endif |
philpem@0 | 250 | |
philpem@0 | 251 | ///////////////////////////////////////////////////// |
philpem@0 | 252 | // Sequential Logic |
philpem@0 | 253 | ///////////////////////////////////////////////////// |
philpem@0 | 254 | |
philpem@0 | 255 | // Toggle a flag when a JTAG write occurs |
philpem@0 | 256 | |
philpem@0 | 257 | always @(negedge jtag_update `CFG_RESET_SENSITIVITY) |
philpem@0 | 258 | begin |
philpem@0 | 259 | if (rst_i == `TRUE) |
philpem@26 | 260 | rx_toggle <= #1 1'b0; |
philpem@0 | 261 | else |
philpem@26 | 262 | rx_toggle <= #1 ~rx_toggle; |
philpem@0 | 263 | end |
philpem@0 | 264 | |
philpem@0 | 265 | always @(*) |
philpem@0 | 266 | begin |
philpem@0 | 267 | rx_byte = jtag_reg_q; |
philpem@0 | 268 | rx_addr = jtag_reg_addr_q; |
philpem@0 | 269 | end |
philpem@0 | 270 | |
philpem@0 | 271 | // Clock domain crossing from JTAG clock domain to CPU clock domain |
philpem@0 | 272 | always @(posedge clk_i `CFG_RESET_SENSITIVITY) |
philpem@0 | 273 | begin |
philpem@0 | 274 | if (rst_i == `TRUE) |
philpem@0 | 275 | begin |
philpem@26 | 276 | rx_toggle_r <= #1 1'b0; |
philpem@26 | 277 | rx_toggle_r_r <= #1 1'b0; |
philpem@26 | 278 | rx_toggle_r_r_r <= #1 1'b0; |
philpem@0 | 279 | end |
philpem@0 | 280 | else |
philpem@0 | 281 | begin |
philpem@26 | 282 | rx_toggle_r <= #1 rx_toggle; |
philpem@26 | 283 | rx_toggle_r_r <= #1 rx_toggle_r; |
philpem@26 | 284 | rx_toggle_r_r_r <= #1 rx_toggle_r_r; |
philpem@0 | 285 | end |
philpem@0 | 286 | end |
philpem@0 | 287 | |
philpem@0 | 288 | // LM32 debug protocol state machine |
philpem@0 | 289 | always @(posedge clk_i `CFG_RESET_SENSITIVITY) |
philpem@0 | 290 | begin |
philpem@0 | 291 | if (rst_i == `TRUE) |
philpem@0 | 292 | begin |
philpem@26 | 293 | state <= #1 `LM32_JTAG_STATE_READ_COMMAND; |
philpem@26 | 294 | command <= #1 4'b0000; |
philpem@26 | 295 | jtag_reg_d <= #1 8'h00; |
philpem@0 | 296 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@26 | 297 | processing <= #1 `FALSE; |
philpem@26 | 298 | jtag_csr_write_enable <= #1 `FALSE; |
philpem@26 | 299 | jtag_read_enable <= #1 `FALSE; |
philpem@26 | 300 | jtag_write_enable <= #1 `FALSE; |
philpem@0 | 301 | `endif |
philpem@0 | 302 | `ifdef CFG_DEBUG_ENABLED |
philpem@26 | 303 | jtag_break <= #1 `FALSE; |
philpem@26 | 304 | jtag_reset <= #1 `FALSE; |
philpem@0 | 305 | `endif |
philpem@0 | 306 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@26 | 307 | uart_tx_byte <= #1 8'h00; |
philpem@26 | 308 | uart_tx_valid <= #1 `FALSE; |
philpem@26 | 309 | uart_rx_byte <= #1 8'h00; |
philpem@26 | 310 | uart_rx_valid <= #1 `FALSE; |
philpem@0 | 311 | `endif |
philpem@0 | 312 | end |
philpem@0 | 313 | else |
philpem@0 | 314 | begin |
philpem@0 | 315 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 316 | if ((csr_write_enable == `TRUE) && (stall_x == `FALSE)) |
philpem@0 | 317 | begin |
philpem@0 | 318 | case (csr) |
philpem@0 | 319 | `LM32_CSR_JTX: |
philpem@0 | 320 | begin |
philpem@0 | 321 | // Set flag indicating data is available |
philpem@26 | 322 | uart_tx_byte <= #1 csr_write_data[`LM32_BYTE_0_RNG]; |
philpem@26 | 323 | uart_tx_valid <= #1 `TRUE; |
philpem@0 | 324 | end |
philpem@0 | 325 | `LM32_CSR_JRX: |
philpem@0 | 326 | begin |
philpem@0 | 327 | // Clear flag indidicating data has been received |
philpem@26 | 328 | uart_rx_valid <= #1 `FALSE; |
philpem@0 | 329 | end |
philpem@0 | 330 | endcase |
philpem@0 | 331 | end |
philpem@0 | 332 | `endif |
philpem@0 | 333 | `ifdef CFG_DEBUG_ENABLED |
philpem@0 | 334 | // When an exception has occured, clear the requests |
philpem@0 | 335 | if (exception_q_w == `TRUE) |
philpem@0 | 336 | begin |
philpem@26 | 337 | jtag_break <= #1 `FALSE; |
philpem@26 | 338 | jtag_reset <= #1 `FALSE; |
philpem@0 | 339 | end |
philpem@0 | 340 | `endif |
philpem@0 | 341 | case (state) |
philpem@0 | 342 | `LM32_JTAG_STATE_READ_COMMAND: |
philpem@0 | 343 | begin |
philpem@0 | 344 | // Wait for rx register to toggle which indicates new data is available |
philpem@0 | 345 | if (rx_toggle_r_r != rx_toggle_r_r_r) |
philpem@0 | 346 | begin |
philpem@26 | 347 | command <= #1 rx_byte[7:4]; |
philpem@0 | 348 | case (rx_addr) |
philpem@0 | 349 | `ifdef CFG_DEBUG_ENABLED |
philpem@0 | 350 | `LM32_DP: |
philpem@0 | 351 | begin |
philpem@0 | 352 | case (rx_byte[7:4]) |
philpem@0 | 353 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 354 | `LM32_DP_READ_MEMORY: |
philpem@26 | 355 | state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; |
philpem@0 | 356 | `LM32_DP_READ_SEQUENTIAL: |
philpem@0 | 357 | begin |
philpem@26 | 358 | {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; |
philpem@26 | 359 | state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; |
philpem@0 | 360 | end |
philpem@0 | 361 | `LM32_DP_WRITE_MEMORY: |
philpem@26 | 362 | state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; |
philpem@0 | 363 | `LM32_DP_WRITE_SEQUENTIAL: |
philpem@0 | 364 | begin |
philpem@26 | 365 | {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; |
philpem@26 | 366 | state <= #1 5; |
philpem@0 | 367 | end |
philpem@0 | 368 | `LM32_DP_WRITE_CSR: |
philpem@26 | 369 | state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; |
philpem@0 | 370 | `endif |
philpem@0 | 371 | `LM32_DP_BREAK: |
philpem@0 | 372 | begin |
philpem@0 | 373 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@26 | 374 | uart_rx_valid <= #1 `FALSE; |
philpem@26 | 375 | uart_tx_valid <= #1 `FALSE; |
philpem@0 | 376 | `endif |
philpem@26 | 377 | jtag_break <= #1 `TRUE; |
philpem@0 | 378 | end |
philpem@0 | 379 | `LM32_DP_RESET: |
philpem@0 | 380 | begin |
philpem@0 | 381 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@26 | 382 | uart_rx_valid <= #1 `FALSE; |
philpem@26 | 383 | uart_tx_valid <= #1 `FALSE; |
philpem@0 | 384 | `endif |
philpem@26 | 385 | jtag_reset <= #1 `TRUE; |
philpem@0 | 386 | end |
philpem@0 | 387 | endcase |
philpem@0 | 388 | end |
philpem@0 | 389 | `endif |
philpem@0 | 390 | `ifdef CFG_JTAG_UART_ENABLED |
philpem@0 | 391 | `LM32_TX: |
philpem@0 | 392 | begin |
philpem@26 | 393 | uart_rx_byte <= #1 rx_byte; |
philpem@26 | 394 | uart_rx_valid <= #1 `TRUE; |
philpem@0 | 395 | end |
philpem@0 | 396 | `LM32_RX: |
philpem@0 | 397 | begin |
philpem@26 | 398 | jtag_reg_d <= #1 uart_tx_byte; |
philpem@26 | 399 | uart_tx_valid <= #1 `FALSE; |
philpem@0 | 400 | end |
philpem@0 | 401 | `endif |
philpem@0 | 402 | default: |
philpem@0 | 403 | ; |
philpem@0 | 404 | endcase |
philpem@0 | 405 | end |
philpem@0 | 406 | end |
philpem@0 | 407 | `ifdef CFG_HW_DEBUG_ENABLED |
philpem@0 | 408 | `LM32_JTAG_STATE_READ_BYTE_0: |
philpem@0 | 409 | begin |
philpem@0 | 410 | if (rx_toggle_r_r != rx_toggle_r_r_r) |
philpem@0 | 411 | begin |
philpem@26 | 412 | jtag_byte_0 <= #1 rx_byte; |
philpem@26 | 413 | state <= #1 `LM32_JTAG_STATE_READ_BYTE_1; |
philpem@0 | 414 | end |
philpem@0 | 415 | end |
philpem@0 | 416 | `LM32_JTAG_STATE_READ_BYTE_1: |
philpem@0 | 417 | begin |
philpem@0 | 418 | if (rx_toggle_r_r != rx_toggle_r_r_r) |
philpem@0 | 419 | begin |
philpem@26 | 420 | jtag_byte_1 <= #1 rx_byte; |
philpem@26 | 421 | state <= #1 `LM32_JTAG_STATE_READ_BYTE_2; |
philpem@0 | 422 | end |
philpem@0 | 423 | end |
philpem@0 | 424 | `LM32_JTAG_STATE_READ_BYTE_2: |
philpem@0 | 425 | begin |
philpem@0 | 426 | if (rx_toggle_r_r != rx_toggle_r_r_r) |
philpem@0 | 427 | begin |
philpem@26 | 428 | jtag_byte_2 <= #1 rx_byte; |
philpem@26 | 429 | state <= #1 `LM32_JTAG_STATE_READ_BYTE_3; |
philpem@0 | 430 | end |
philpem@0 | 431 | end |
philpem@0 | 432 | `LM32_JTAG_STATE_READ_BYTE_3: |
philpem@0 | 433 | begin |
philpem@0 | 434 | if (rx_toggle_r_r != rx_toggle_r_r_r) |
philpem@0 | 435 | begin |
philpem@26 | 436 | jtag_byte_3 <= #1 rx_byte; |
philpem@0 | 437 | if (command == `LM32_DP_READ_MEMORY) |
philpem@26 | 438 | state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; |
philpem@0 | 439 | else |
philpem@26 | 440 | state <= #1 `LM32_JTAG_STATE_READ_BYTE_4; |
philpem@0 | 441 | end |
philpem@0 | 442 | end |
philpem@0 | 443 | `LM32_JTAG_STATE_READ_BYTE_4: |
philpem@0 | 444 | begin |
philpem@0 | 445 | if (rx_toggle_r_r != rx_toggle_r_r_r) |
philpem@0 | 446 | begin |
philpem@26 | 447 | jtag_byte_4 <= #1 rx_byte; |
philpem@26 | 448 | state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; |
philpem@0 | 449 | end |
philpem@0 | 450 | end |
philpem@0 | 451 | `LM32_JTAG_STATE_PROCESS_COMMAND: |
philpem@0 | 452 | begin |
philpem@0 | 453 | case (command) |
philpem@0 | 454 | `LM32_DP_READ_MEMORY, |
philpem@0 | 455 | `LM32_DP_READ_SEQUENTIAL: |
philpem@0 | 456 | begin |
philpem@26 | 457 | jtag_read_enable <= #1 `TRUE; |
philpem@26 | 458 | processing <= #1 `TRUE; |
philpem@26 | 459 | state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; |
philpem@0 | 460 | end |
philpem@0 | 461 | `LM32_DP_WRITE_MEMORY, |
philpem@0 | 462 | `LM32_DP_WRITE_SEQUENTIAL: |
philpem@0 | 463 | begin |
philpem@26 | 464 | jtag_write_enable <= #1 `TRUE; |
philpem@26 | 465 | processing <= #1 `TRUE; |
philpem@26 | 466 | state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; |
philpem@0 | 467 | end |
philpem@0 | 468 | `LM32_DP_WRITE_CSR: |
philpem@0 | 469 | begin |
philpem@26 | 470 | jtag_csr_write_enable <= #1 `TRUE; |
philpem@26 | 471 | processing <= #1 `TRUE; |
philpem@26 | 472 | state <= #1 `LM32_JTAG_STATE_WAIT_FOR_CSR; |
philpem@0 | 473 | end |
philpem@0 | 474 | endcase |
philpem@0 | 475 | end |
philpem@0 | 476 | `LM32_JTAG_STATE_WAIT_FOR_MEMORY: |
philpem@0 | 477 | begin |
philpem@0 | 478 | if (jtag_access_complete == `TRUE) |
philpem@0 | 479 | begin |
philpem@26 | 480 | jtag_read_enable <= #1 `FALSE; |
philpem@26 | 481 | jtag_reg_d <= #1 jtag_read_data; |
philpem@26 | 482 | jtag_write_enable <= #1 `FALSE; |
philpem@26 | 483 | processing <= #1 `FALSE; |
philpem@26 | 484 | state <= #1 `LM32_JTAG_STATE_READ_COMMAND; |
philpem@0 | 485 | end |
philpem@0 | 486 | end |
philpem@0 | 487 | `LM32_JTAG_STATE_WAIT_FOR_CSR: |
philpem@0 | 488 | begin |
philpem@26 | 489 | jtag_csr_write_enable <= #1 `FALSE; |
philpem@26 | 490 | processing <= #1 `FALSE; |
philpem@26 | 491 | state <= #1 `LM32_JTAG_STATE_READ_COMMAND; |
philpem@0 | 492 | end |
philpem@0 | 493 | `endif |
philpem@0 | 494 | endcase |
philpem@0 | 495 | end |
philpem@0 | 496 | end |
philpem@0 | 497 | |
philpem@0 | 498 | endmodule |
philpem@0 | 499 | |
philpem@0 | 500 | `endif |