spiprog.v

Mon, 05 Apr 2010 20:23:04 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 05 Apr 2010 20:23:04 +0100
changeset 4
99b7b037ce82
parent 0
cd0b58aa6f83
child 26
73de224304c1
permissions
-rw-r--r--

add better comment re Xilinx Xst cache issues

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : SPIPROG.v
philpem@0 19 // This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
philpem@0 20 // core. There are only three ER2 registers, one control register and two
philpem@0 21 // data registers, in this IP core. The control register is a 8-bit wide
philpem@0 22 // register for selecting which data register will be accessed when the
philpem@0 23 // Control/Data# bit in ER1 register is low. Data register 0 is a readonly
philpem@0 24 // ID register. It is composed of three register fields -- an 8-bit
philpem@0 25 // "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
philpem@0 26 // Data register 1 is a variable length register for sending commands to or
philpem@0 27 // receiving readback data from the SPI Serial FLASH device.
philpem@0 28 // Dependencies : None
philpem@0 29 // Version : 6.1.17
philpem@0 30 // 1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
philpem@0 31 // 2. Same as TYPEA and TYPEB modules, use falling edge clock
philpem@0 32 // for all TCK Flip-Flops.
philpem@0 33 // 3. Added 7 delay Flip-Flops so that the DR1 readback data from
philpem@0 34 // SPI Serial FLASH is in the byte boundary.
philpem@0 35 // Version : 7.0SP2, 3.0
philpem@0 36 // : No Change
philpem@0 37 // Version : 3.1
philpem@0 38 // : No Change
philpem@0 39 // =============================================================================
philpem@0 40 //---------------------------------------------------------------------------
philpem@0 41 //
philpem@0 42 //Name : SPIPROG.v
philpem@0 43 //
philpem@0 44 //Description:
philpem@0 45 //
philpem@0 46 // This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
philpem@0 47 // core. There are only three ER2 registers, one control register and two
philpem@0 48 // data registers, in this IP core. The control register is a 8-bit wide
philpem@0 49 // register for selecting which data register will be accessed when the
philpem@0 50 // Control/Data# bit in ER1 register is low. Data register 0 is a readonly
philpem@0 51 // ID register. It is composed of three register fields -- an 8-bit
philpem@0 52 // "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
philpem@0 53 // Data register 1 is a variable length register for sending commands to or
philpem@0 54 // receiving readback data from the SPI Serial FLASH device.
philpem@0 55 //
philpem@0 56 //$Log: spiprog.vhd,v $
philpem@0 57 //Revision 1.2 2004-09-09 11:43:26-07 jhsin
philpem@0 58 //1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
philpem@0 59 //2. Same as TYPEA and TYPEB modules, use falling edge clock
philpem@0 60 // for all TCK Flip-Flops.
philpem@0 61 //
philpem@0 62 //Revision 1.1 2004-08-12 13:22:05-07 jhsin
philpem@0 63 //Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary.
philpem@0 64 //
philpem@0 65 //Revision 1.0 2004-08-03 18:35:56-07 jhsin
philpem@0 66 //Initial revision
philpem@0 67 //
philpem@0 68 //
philpem@0 69
philpem@0 70 module SPIPROG (input JTCK ,
philpem@0 71 input JTDI ,
philpem@0 72 output JTDO2 ,
philpem@0 73 input JSHIFT ,
philpem@0 74 input JUPDATE ,
philpem@0 75 input JRSTN ,
philpem@0 76 input JCE2 ,
philpem@0 77 input SPIPROG_ENABLE ,
philpem@0 78 input CONTROL_DATAN ,
philpem@0 79 output SPI_C ,
philpem@0 80 output SPI_D ,
philpem@0 81 output SPI_SN ,
philpem@0 82 input SPI_Q);
philpem@0 83
philpem@0 84 wire er2Cr_enable ;
philpem@0 85 wire er2Dr0_enable;
philpem@0 86 wire er2Dr1_enable;
philpem@0 87
philpem@0 88 wire tdo_er2Cr ;
philpem@0 89 wire tdo_er2Dr0;
philpem@0 90 wire tdo_er2Dr1;
philpem@0 91
philpem@0 92 wire [7:0] encodedDrSelBits ;
philpem@0 93 wire [8:0] er2CrTdiBit ;
philpem@0 94 wire [8:0] er2Dr0TdiBit ;
philpem@0 95
philpem@0 96 wire captureDrER2;
philpem@0 97 reg spi_s ;
philpem@0 98 reg [6:0] spi_q_dly;
philpem@0 99
philpem@0 100 wire [7:0] ip_functionality_id;
philpem@0 101
philpem@0 102 genvar i;
philpem@0 103
philpem@0 104 // ------ Control Register 0 ------
philpem@0 105
philpem@0 106 assign er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN;
philpem@0 107
philpem@0 108 assign tdo_er2Cr = er2CrTdiBit[0];
philpem@0 109
philpem@0 110 // CR_BIT0_BIT7
philpem@0 111 generate
philpem@0 112 for(i=0; i<=7; i=i+1)
philpem@0 113 begin:CR_BIT0_BIT7
philpem@0 114 TYPEA BIT_N (.CLK (JTCK),
philpem@0 115 .RESET_N (JRSTN),
philpem@0 116 .CLKEN (er2Cr_enable),
philpem@0 117 .TDI (er2CrTdiBit[i + 1]),
philpem@0 118 .TDO (er2CrTdiBit[i]),
philpem@0 119 .DATA_OUT (encodedDrSelBits[i]),
philpem@0 120 .DATA_IN (encodedDrSelBits[i]),
philpem@0 121 .CAPTURE_DR (captureDrER2),
philpem@0 122 .UPDATE_DR (JUPDATE));
philpem@0 123 end
philpem@0 124 endgenerate // CR_BIT0_BIT7
philpem@0 125
philpem@0 126 assign er2CrTdiBit[8] = JTDI;
philpem@0 127
philpem@0 128 // ------ Data Register 0 ------
philpem@0 129 assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0;
philpem@0 130
philpem@0 131 assign tdo_er2Dr0 = er2Dr0TdiBit[0];
philpem@0 132
philpem@0 133 assign ip_functionality_id = 8'b00000001; //-- SPI Serial FLASH Programmer (0x01)
philpem@0 134
philpem@0 135 // DR0_BIT0_BIT7
philpem@0 136 generate
philpem@0 137 for(i=0; i<=7; i=i+1)
philpem@0 138 begin:DR0_BIT0_BIT7
philpem@0 139 TYPEB BIT_N (.CLK (JTCK),
philpem@0 140 .RESET_N (JRSTN),
philpem@0 141 .CLKEN (er2Dr0_enable),
philpem@0 142 .TDI (er2Dr0TdiBit[i + 1]),
philpem@0 143 .TDO (er2Dr0TdiBit[i]),
philpem@0 144 .DATA_IN (ip_functionality_id[i]),
philpem@0 145 .CAPTURE_DR (captureDrER2));
philpem@0 146 end
philpem@0 147 endgenerate // DR0_BIT0_BIT7
philpem@0 148
philpem@0 149 assign er2Dr0TdiBit[8] = JTDI;
philpem@0 150
philpem@0 151 // ------ Data Register 1 ------
philpem@0 152
philpem@0 153 assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ? 1'b1 : 1'b0;
philpem@0 154
philpem@0 155 assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s);
philpem@0 156
philpem@0 157 assign SPI_D = JTDI & er2Dr1_enable;
philpem@0 158
philpem@0 159 // SPI_S_Proc
philpem@0 160 always @(negedge JTCK or negedge JRSTN)
philpem@0 161 begin
philpem@0 162 if (~JRSTN)
philpem@0 163 spi_s <= 1'b0;
philpem@0 164 else
philpem@0 165 if (JUPDATE)
philpem@0 166 spi_s <= 1'b0;
philpem@0 167 else
philpem@0 168 spi_s <= er2Dr1_enable;
philpem@0 169 end
philpem@0 170
philpem@0 171 assign SPI_SN = ~spi_s;
philpem@0 172
philpem@0 173 // SPI_Q_Proc
philpem@0 174 always @(negedge JTCK or negedge JRSTN)
philpem@0 175 begin
philpem@0 176 if (~JRSTN)
philpem@0 177 spi_q_dly <= 'b0;
philpem@0 178 else
philpem@0 179 if (er2Dr1_enable)
philpem@0 180 spi_q_dly <= {spi_q_dly[5:0],SPI_Q};
philpem@0 181 end
philpem@0 182
philpem@0 183 assign tdo_er2Dr1 = spi_q_dly[6];
philpem@0 184
philpem@0 185 // ------ JTDO2 MUX ------
philpem@0 186
philpem@0 187 assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr :
philpem@0 188 (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 :
philpem@0 189 (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0;
philpem@0 190
philpem@0 191 assign captureDrER2 = ~JSHIFT & JCE2;
philpem@0 192
philpem@0 193 endmodule