typeb.v

Mon, 05 Apr 2010 20:23:04 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 05 Apr 2010 20:23:04 +0100
changeset 4
99b7b037ce82
parent 0
cd0b58aa6f83
child 26
73de224304c1
permissions
-rw-r--r--

add better comment re Xilinx Xst cache issues

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : TYPEB.v
philpem@0 19 // Description:
philpem@0 20 // This is one of the two types of cells that are used to create ER1/ER2
philpem@0 21 // register bits.
philpem@0 22 // Dependencies : None
philpem@0 23 // Version : 6.1.17
philpem@0 24 // Modified typeb module to remove redundant DATA_OUT port.
philpem@0 25 // Version : 7.0SP2, 3.0
philpem@0 26 // : No Change
philpem@0 27 // Version : 3.1
philpem@0 28 // : No Change
philpem@0 29 // =============================================================================
philpem@0 30 module TYPEB
philpem@0 31 (
philpem@0 32 input CLK,
philpem@0 33 input RESET_N,
philpem@0 34 input CLKEN,
philpem@0 35 input TDI,
philpem@0 36 output TDO,
philpem@0 37 input DATA_IN,
philpem@0 38 input CAPTURE_DR
philpem@0 39 );
philpem@0 40
philpem@0 41 reg tdoInt;
philpem@0 42
philpem@0 43 always @ (negedge CLK or negedge RESET_N)
philpem@0 44 begin
philpem@0 45 if (RESET_N== 1'b0)
philpem@0 46 tdoInt <= 1'b0;
philpem@0 47 else if (CLK == 1'b0)
philpem@0 48 if (CLKEN==1'b1)
philpem@0 49 if (CAPTURE_DR==1'b0)
philpem@0 50 tdoInt <= TDI;
philpem@0 51 else
philpem@0 52 tdoInt <= DATA_IN;
philpem@0 53 end
philpem@0 54
philpem@0 55 assign TDO = tdoInt;
philpem@0 56
philpem@0 57 endmodule
philpem@0 58