lm32_icache.v

Sun, 04 Apr 2010 20:52:32 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 04 Apr 2010 20:52:32 +0100
changeset 2
a61bb364ae1f
parent 0
cd0b58aa6f83
child 3
b153470d41c5
permissions
-rw-r--r--

Disable Lattice-specific stuff by default

To build on Lattice platforms, `define PLATFORM_LATTICE in lm32_include.v.
Otherwise, non-optimal "platform independent" HDL will be used.
This means LM32 can now be built for non-Lattice FPGAs.

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : lm32_icache.v
philpem@0 19 // Title : Instruction cache
philpem@0 20 // Dependencies : lm32_include.v
philpem@0 21 //
philpem@0 22 // Version 3.5
philpem@0 23 // 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
philpem@0 24 // cause segmentation fault due to incorrect fetches.
philpem@0 25 //
philpem@0 26 // Version 3.1
philpem@0 27 // 1. Feature: Support for user-selected resource usage when implementing
philpem@0 28 // cache memory. Additional parameters must be defined when invoking module
philpem@0 29 // lm32_ram. Instruction cache miss mechanism is dependent on branch
philpem@0 30 // prediction being performed in D stage of pipeline.
philpem@0 31 //
philpem@0 32 // Version 7.0SP2, 3.0
philpem@0 33 // No change
philpem@0 34 // =============================================================================
philpem@0 35
philpem@0 36 `include "lm32_include.v"
philpem@0 37
philpem@0 38 `ifdef CFG_ICACHE_ENABLED
philpem@0 39
philpem@0 40 `define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
philpem@0 41 `define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
philpem@0 42 `define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
philpem@0 43 `define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
philpem@0 44
philpem@0 45 `define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
philpem@0 46 `define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
philpem@0 47 `define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
philpem@0 48 `define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
philpem@0 49
philpem@0 50 `define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
philpem@0 51 `define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
philpem@0 52 `define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
philpem@0 53 `define LM32_IC_TAGS_VALID_RNG 0
philpem@0 54
philpem@0 55 `define LM32_IC_STATE_RNG 3:0
philpem@0 56 `define LM32_IC_STATE_FLUSH_INIT 4'b0001
philpem@0 57 `define LM32_IC_STATE_FLUSH 4'b0010
philpem@0 58 `define LM32_IC_STATE_CHECK 4'b0100
philpem@0 59 `define LM32_IC_STATE_REFILL 4'b1000
philpem@0 60
philpem@0 61 /////////////////////////////////////////////////////
philpem@0 62 // Module interface
philpem@0 63 /////////////////////////////////////////////////////
philpem@0 64
philpem@0 65 module lm32_icache (
philpem@0 66 // ----- Inputs -----
philpem@0 67 clk_i,
philpem@0 68 rst_i,
philpem@0 69 stall_a,
philpem@0 70 stall_f,
philpem@0 71 address_a,
philpem@0 72 address_f,
philpem@0 73 read_enable_f,
philpem@0 74 refill_ready,
philpem@0 75 refill_data,
philpem@0 76 iflush,
philpem@0 77 `ifdef CFG_IROM_ENABLED
philpem@0 78 select_f,
philpem@0 79 `endif
philpem@0 80 valid_d,
philpem@0 81 branch_predict_taken_d,
philpem@0 82 // ----- Outputs -----
philpem@0 83 stall_request,
philpem@0 84 restart_request,
philpem@0 85 refill_request,
philpem@0 86 refill_address,
philpem@0 87 refilling,
philpem@0 88 inst
philpem@0 89 );
philpem@0 90
philpem@0 91 /////////////////////////////////////////////////////
philpem@0 92 // Parameters
philpem@0 93 /////////////////////////////////////////////////////
philpem@0 94
philpem@0 95 parameter associativity = 1; // Associativity of the cache (Number of ways)
philpem@0 96 parameter sets = 512; // Number of sets
philpem@0 97 parameter bytes_per_line = 16; // Number of bytes per cache line
philpem@0 98 parameter base_address = 0; // Base address of cachable memory
philpem@0 99 parameter limit = 0; // Limit (highest address) of cachable memory
philpem@0 100
philpem@0 101 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
philpem@0 102 localparam addr_set_width = clogb2(sets)-1;
philpem@0 103 localparam addr_offset_lsb = 2;
philpem@0 104 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
philpem@0 105 localparam addr_set_lsb = (addr_offset_msb+1);
philpem@0 106 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
philpem@0 107 localparam addr_tag_lsb = (addr_set_msb+1);
philpem@0 108 localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
philpem@0 109 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
philpem@0 110
philpem@0 111 /////////////////////////////////////////////////////
philpem@0 112 // Inputs
philpem@0 113 /////////////////////////////////////////////////////
philpem@0 114
philpem@0 115 input clk_i; // Clock
philpem@0 116 input rst_i; // Reset
philpem@0 117
philpem@0 118 input stall_a; // Stall instruction in A stage
philpem@0 119 input stall_f; // Stall instruction in F stage
philpem@0 120
philpem@0 121 input valid_d; // Valid instruction in D stage
philpem@0 122 input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken
philpem@0 123
philpem@0 124 input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
philpem@0 125 input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
philpem@0 126 input read_enable_f; // Indicates if cache access is valid
philpem@0 127
philpem@0 128 input refill_ready; // Next word of refill data is ready
philpem@0 129 input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
philpem@0 130
philpem@0 131 input iflush; // Flush the cache
philpem@0 132 `ifdef CFG_IROM_ENABLED
philpem@0 133 input select_f; // Instruction in F stage is mapped through instruction cache
philpem@0 134 `endif
philpem@0 135
philpem@0 136 /////////////////////////////////////////////////////
philpem@0 137 // Outputs
philpem@0 138 /////////////////////////////////////////////////////
philpem@0 139
philpem@0 140 output stall_request; // Request to stall the pipeline
philpem@0 141 wire stall_request;
philpem@0 142 output restart_request; // Request to restart instruction that caused the cache miss
philpem@0 143 reg restart_request;
philpem@0 144 output refill_request; // Request to refill a cache line
philpem@0 145 wire refill_request;
philpem@0 146 output [`LM32_PC_RNG] refill_address; // Base address of cache refill
philpem@0 147 reg [`LM32_PC_RNG] refill_address;
philpem@0 148 output refilling; // Indicates the instruction cache is currently refilling
philpem@0 149 reg refilling;
philpem@0 150 output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
philpem@0 151 wire [`LM32_INSTRUCTION_RNG] inst;
philpem@0 152
philpem@0 153 /////////////////////////////////////////////////////
philpem@0 154 // Internal nets and registers
philpem@0 155 /////////////////////////////////////////////////////
philpem@0 156
philpem@0 157 wire enable;
philpem@0 158 wire [0:associativity-1] way_mem_we;
philpem@0 159 wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
philpem@0 160 wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
philpem@0 161 wire [0:associativity-1] way_valid;
philpem@0 162 wire [0:associativity-1] way_match;
philpem@0 163 wire miss;
philpem@0 164
philpem@0 165 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
philpem@0 166 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
philpem@0 167 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
philpem@0 168 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
philpem@0 169 wire [`LM32_IC_TAGS_RNG] tmem_write_data;
philpem@0 170
philpem@0 171 reg [`LM32_IC_STATE_RNG] state;
philpem@0 172 wire flushing;
philpem@0 173 wire check;
philpem@0 174 wire refill;
philpem@0 175
philpem@0 176 reg [associativity-1:0] refill_way_select;
philpem@0 177 reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
philpem@0 178 wire last_refill;
philpem@0 179 reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
philpem@0 180
philpem@0 181 genvar i;
philpem@0 182
philpem@0 183 /////////////////////////////////////////////////////
philpem@0 184 // Functions
philpem@0 185 /////////////////////////////////////////////////////
philpem@0 186
philpem@0 187 `include "lm32_functions.v"
philpem@0 188
philpem@0 189 /////////////////////////////////////////////////////
philpem@0 190 // Instantiations
philpem@0 191 /////////////////////////////////////////////////////
philpem@0 192
philpem@0 193 generate
philpem@0 194 for (i = 0; i < associativity; i = i + 1)
philpem@0 195 begin : memories
philpem@0 196
philpem@0 197 lm32_ram
philpem@0 198 #(
philpem@0 199 // ----- Parameters -------
philpem@0 200 .data_width (32),
philpem@0 201 .address_width (`LM32_IC_DMEM_ADDR_WIDTH),
philpem@2 202 `ifdef PLATFORM_LATTICE
philpem@2 203 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
philpem@0 204 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 205 .RAM_TYPE ("RAM_DP_TRUE")
philpem@2 206 `else
philpem@2 207 `ifdef CFG_ICACHE_DAT_USE_DP
philpem@0 208 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 209 .RAM_TYPE ("RAM_DP")
philpem@2 210 `else
philpem@2 211 `ifdef CFG_ICACHE_DAT_USE_SLICE
philpem@0 212 .RAM_IMPLEMENTATION ("SLICE")
philpem@2 213 `else
philpem@0 214 .RAM_IMPLEMENTATION ("AUTO")
philpem@2 215 `endif
philpem@0 216 `endif
philpem@0 217 `endif
philpem@0 218 `endif
philpem@0 219 )
philpem@0 220 way_0_data_ram
philpem@0 221 (
philpem@0 222 // ----- Inputs -------
philpem@0 223 .read_clk (clk_i),
philpem@0 224 .write_clk (clk_i),
philpem@0 225 .reset (rst_i),
philpem@0 226 .read_address (dmem_read_address),
philpem@0 227 .enable_read (enable),
philpem@0 228 .write_address (dmem_write_address),
philpem@0 229 .enable_write (`TRUE),
philpem@0 230 .write_enable (way_mem_we[i]),
philpem@0 231 .write_data (refill_data),
philpem@0 232 // ----- Outputs -------
philpem@0 233 .read_data (way_data[i])
philpem@0 234 );
philpem@0 235
philpem@0 236 lm32_ram
philpem@0 237 #(
philpem@0 238 // ----- Parameters -------
philpem@0 239 .data_width (`LM32_IC_TAGS_WIDTH),
philpem@0 240 .address_width (`LM32_IC_TMEM_ADDR_WIDTH),
philpem@0 241 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
philpem@0 242 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 243 .RAM_TYPE ("RAM_DP_TRUE")
philpem@0 244 `else
philpem@0 245 `ifdef CFG_ICACHE_DAT_USE_DP
philpem@0 246 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 247 .RAM_TYPE ("RAM_DP")
philpem@0 248 `else
philpem@0 249 `ifdef CFG_ICACHE_DAT_USE_SLICE
philpem@0 250 .RAM_IMPLEMENTATION ("SLICE")
philpem@0 251 `else
philpem@0 252 .RAM_IMPLEMENTATION ("AUTO")
philpem@0 253 `endif
philpem@0 254 `endif
philpem@0 255 `endif
philpem@0 256 )
philpem@0 257 way_0_tag_ram
philpem@0 258 (
philpem@0 259 // ----- Inputs -------
philpem@0 260 .read_clk (clk_i),
philpem@0 261 .write_clk (clk_i),
philpem@0 262 .reset (rst_i),
philpem@0 263 .read_address (tmem_read_address),
philpem@0 264 .enable_read (enable),
philpem@0 265 .write_address (tmem_write_address),
philpem@0 266 .enable_write (`TRUE),
philpem@0 267 .write_enable (way_mem_we[i] | flushing),
philpem@0 268 .write_data (tmem_write_data),
philpem@0 269 // ----- Outputs -------
philpem@0 270 .read_data ({way_tag[i], way_valid[i]})
philpem@0 271 );
philpem@0 272
philpem@0 273 end
philpem@0 274 endgenerate
philpem@0 275
philpem@0 276 /////////////////////////////////////////////////////
philpem@0 277 // Combinational logic
philpem@0 278 /////////////////////////////////////////////////////
philpem@0 279
philpem@0 280 // Compute which ways in the cache match the address address being read
philpem@0 281 generate
philpem@0 282 for (i = 0; i < associativity; i = i + 1)
philpem@0 283 begin : match
philpem@0 284 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
philpem@0 285 end
philpem@0 286 endgenerate
philpem@0 287
philpem@0 288 // Select data from way that matched the address being read
philpem@0 289 generate
philpem@0 290 if (associativity == 1)
philpem@0 291 begin : inst_1
philpem@0 292 assign inst = way_match[0] ? way_data[0] : 32'b0;
philpem@0 293 end
philpem@0 294 else if (associativity == 2)
philpem@0 295 begin : inst_2
philpem@0 296 assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
philpem@0 297 end
philpem@0 298 endgenerate
philpem@0 299
philpem@0 300 // Compute address to use to index into the data memories
philpem@0 301 generate
philpem@0 302 if (bytes_per_line > 4)
philpem@0 303 assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
philpem@0 304 else
philpem@0 305 assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
philpem@0 306 endgenerate
philpem@0 307
philpem@0 308 assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
philpem@0 309
philpem@0 310 // Compute address to use to index into the tag memories
philpem@0 311 assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
philpem@0 312 assign tmem_write_address = flushing
philpem@0 313 ? flush_set
philpem@0 314 : refill_address[`LM32_IC_ADDR_SET_RNG];
philpem@0 315
philpem@0 316 // Compute signal to indicate when we are on the last refill accesses
philpem@0 317 generate
philpem@0 318 if (bytes_per_line > 4)
philpem@0 319 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
philpem@0 320 else
philpem@0 321 assign last_refill = `TRUE;
philpem@0 322 endgenerate
philpem@0 323
philpem@0 324 // Compute data and tag memory access enable
philpem@0 325 assign enable = (stall_a == `FALSE);
philpem@0 326
philpem@0 327 // Compute data and tag memory write enables
philpem@0 328 generate
philpem@0 329 if (associativity == 1)
philpem@0 330 begin : we_1
philpem@0 331 assign way_mem_we[0] = (refill_ready == `TRUE);
philpem@0 332 end
philpem@0 333 else
philpem@0 334 begin : we_2
philpem@0 335 assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
philpem@0 336 assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
philpem@0 337 end
philpem@0 338 endgenerate
philpem@0 339
philpem@0 340 // On the last refill cycle set the valid bit, for all other writes it should be cleared
philpem@0 341 assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
philpem@0 342 assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
philpem@0 343
philpem@0 344 // Signals that indicate which state we are in
philpem@0 345 assign flushing = |state[1:0];
philpem@0 346 assign check = state[2];
philpem@0 347 assign refill = state[3];
philpem@0 348
philpem@0 349 assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
philpem@0 350 assign stall_request = (check == `FALSE);
philpem@0 351 assign refill_request = (refill == `TRUE);
philpem@0 352
philpem@0 353 /////////////////////////////////////////////////////
philpem@0 354 // Sequential logic
philpem@0 355 /////////////////////////////////////////////////////
philpem@0 356
philpem@0 357 // Record way selected for replacement on a cache miss
philpem@0 358 generate
philpem@0 359 if (associativity >= 2)
philpem@0 360 begin : way_select
philpem@0 361 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 362 begin
philpem@0 363 if (rst_i == `TRUE)
philpem@0 364 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
philpem@0 365 else
philpem@0 366 begin
philpem@0 367 if (miss == `TRUE)
philpem@0 368 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
philpem@0 369 end
philpem@0 370 end
philpem@0 371 end
philpem@0 372 endgenerate
philpem@0 373
philpem@0 374 // Record whether we are refilling
philpem@0 375 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 376 begin
philpem@0 377 if (rst_i == `TRUE)
philpem@0 378 refilling <= `FALSE;
philpem@0 379 else
philpem@0 380 refilling <= refill;
philpem@0 381 end
philpem@0 382
philpem@0 383 // Instruction cache control FSM
philpem@0 384 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 385 begin
philpem@0 386 if (rst_i == `TRUE)
philpem@0 387 begin
philpem@0 388 state <= `LM32_IC_STATE_FLUSH_INIT;
philpem@0 389 flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
philpem@0 390 refill_address <= {`LM32_PC_WIDTH{1'bx}};
philpem@0 391 restart_request <= `FALSE;
philpem@0 392 end
philpem@0 393 else
philpem@0 394 begin
philpem@0 395 case (state)
philpem@0 396
philpem@0 397 // Flush the cache for the first time after reset
philpem@0 398 `LM32_IC_STATE_FLUSH_INIT:
philpem@0 399 begin
philpem@0 400 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
philpem@0 401 state <= `LM32_IC_STATE_CHECK;
philpem@0 402 flush_set <= flush_set - 1'b1;
philpem@0 403 end
philpem@0 404
philpem@0 405 // Flush the cache in response to an write to the ICC CSR
philpem@0 406 `LM32_IC_STATE_FLUSH:
philpem@0 407 begin
philpem@0 408 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
philpem@0 409 `ifdef CFG_IROM_ENABLED
philpem@0 410 if (select_f)
philpem@0 411 state <= `LM32_IC_STATE_REFILL;
philpem@0 412 else
philpem@0 413 `endif
philpem@0 414 state <= `LM32_IC_STATE_CHECK;
philpem@0 415
philpem@0 416 flush_set <= flush_set - 1'b1;
philpem@0 417 end
philpem@0 418
philpem@0 419 // Check for cache misses
philpem@0 420 `LM32_IC_STATE_CHECK:
philpem@0 421 begin
philpem@0 422 if (stall_a == `FALSE)
philpem@0 423 restart_request <= `FALSE;
philpem@0 424 if (iflush == `TRUE)
philpem@0 425 begin
philpem@0 426 refill_address <= address_f;
philpem@0 427 state <= `LM32_IC_STATE_FLUSH;
philpem@0 428 end
philpem@0 429 else if (miss == `TRUE)
philpem@0 430 begin
philpem@0 431 refill_address <= address_f;
philpem@0 432 state <= `LM32_IC_STATE_REFILL;
philpem@0 433 end
philpem@0 434 end
philpem@0 435
philpem@0 436 // Refill a cache line
philpem@0 437 `LM32_IC_STATE_REFILL:
philpem@0 438 begin
philpem@0 439 if (refill_ready == `TRUE)
philpem@0 440 begin
philpem@0 441 if (last_refill == `TRUE)
philpem@0 442 begin
philpem@0 443 restart_request <= `TRUE;
philpem@0 444 state <= `LM32_IC_STATE_CHECK;
philpem@0 445 end
philpem@0 446 end
philpem@0 447 end
philpem@0 448
philpem@0 449 endcase
philpem@0 450 end
philpem@0 451 end
philpem@0 452
philpem@0 453 generate
philpem@0 454 if (bytes_per_line > 4)
philpem@0 455 begin
philpem@0 456 // Refill offset
philpem@0 457 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 458 begin
philpem@0 459 if (rst_i == `TRUE)
philpem@0 460 refill_offset <= {addr_offset_width{1'b0}};
philpem@0 461 else
philpem@0 462 begin
philpem@0 463 case (state)
philpem@0 464
philpem@0 465 // Check for cache misses
philpem@0 466 `LM32_IC_STATE_CHECK:
philpem@0 467 begin
philpem@0 468 if (iflush == `TRUE)
philpem@0 469 refill_offset <= {addr_offset_width{1'b0}};
philpem@0 470 else if (miss == `TRUE)
philpem@0 471 refill_offset <= {addr_offset_width{1'b0}};
philpem@0 472 end
philpem@0 473
philpem@0 474 // Refill a cache line
philpem@0 475 `LM32_IC_STATE_REFILL:
philpem@0 476 begin
philpem@0 477 if (refill_ready == `TRUE)
philpem@0 478 refill_offset <= refill_offset + 1'b1;
philpem@0 479 end
philpem@0 480
philpem@0 481 endcase
philpem@0 482 end
philpem@0 483 end
philpem@0 484 end
philpem@0 485 endgenerate
philpem@0 486
philpem@0 487 endmodule
philpem@0 488
philpem@0 489 `endif
philpem@0 490