typea.v

Sun, 04 Apr 2010 20:52:32 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 04 Apr 2010 20:52:32 +0100
changeset 2
a61bb364ae1f
parent 0
cd0b58aa6f83
child 26
73de224304c1
permissions
-rw-r--r--

Disable Lattice-specific stuff by default

To build on Lattice platforms, `define PLATFORM_LATTICE in lm32_include.v.
Otherwise, non-optimal "platform independent" HDL will be used.
This means LM32 can now be built for non-Lattice FPGAs.

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : TYPEA.v
philpem@0 19 // Description:
philpem@0 20 // This is one of the two types of cells that are used to create ER1/ER2
philpem@0 21 // register bits.
philpem@0 22 // Dependencies : None
philpem@0 23 // Version : 6.1.17
philpem@0 24 // The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the
philpem@0 25 // dedicate logic JTAG_PORT didn't act as what their names implied.
philpem@0 26 // The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR.
philpem@0 27 // The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR.
philpem@0 28 // These had caused a lot of headaches for a long time and now they are
philpem@0 29 // fixed by:
philpem@0 30 // (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create
philpem@0 31 // CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers.
philpem@0 32 // (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals
philpem@0 33 // have the same waveform of ENABLE_ER2) directly to be the CLKEN
philpem@0 34 // of all typeA, typeB bits in the ER1, ER2 registers.
philpem@0 35 // (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable
philpem@0 36 // of the holding flip-flop.
philpem@0 37 // These changes caused ispTracy.vhd and cge.dat changes and the new
philpem@0 38 // CGE.exe version will be 1.3.5.
philpem@0 39 // Version : 7.0SP2, 3.0
philpem@0 40 // : No Change
philpem@0 41 // Version : 3.1
philpem@0 42 // : No Change
philpem@0 43 // =============================================================================
philpem@0 44 module TYPEA(
philpem@0 45 input CLK,
philpem@0 46 input RESET_N,
philpem@0 47 input CLKEN,
philpem@0 48 input TDI,
philpem@0 49 output TDO,
philpem@0 50 output reg DATA_OUT,
philpem@0 51 input DATA_IN,
philpem@0 52 input CAPTURE_DR,
philpem@0 53 input UPDATE_DR
philpem@0 54 );
philpem@0 55
philpem@0 56 reg tdoInt;
philpem@0 57
philpem@0 58
philpem@0 59 always @ (negedge CLK or negedge RESET_N)
philpem@0 60 begin
philpem@0 61 if (RESET_N == 1'b0)
philpem@0 62 tdoInt <= 1'b0;
philpem@0 63 else if (CLK == 1'b0)
philpem@0 64 if (CLKEN == 1'b1)
philpem@0 65 if (CAPTURE_DR == 1'b0)
philpem@0 66 tdoInt <= TDI;
philpem@0 67 else
philpem@0 68 tdoInt <= DATA_IN;
philpem@0 69 end
philpem@0 70
philpem@0 71 assign TDO = tdoInt;
philpem@0 72
philpem@0 73 always @ (negedge CLK or negedge RESET_N)
philpem@0 74 begin
philpem@0 75 if (RESET_N == 1'b0)
philpem@0 76 DATA_OUT <= 1'b0;
philpem@0 77 else if (CLK == 1'b0)
philpem@0 78 if (UPDATE_DR == 1'b1)
philpem@0 79 DATA_OUT <= tdoInt;
philpem@0 80 end
philpem@0 81 endmodule