lm32_include.v

Mon, 05 Apr 2010 21:00:31 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 05 Apr 2010 21:00:31 +0100
changeset 6
a8e459b24c31
parent 5
35ebde37101f
child 7
0a26167af7e1
permissions
-rw-r--r--

reduce size of caches to fit in DE1 FPGA

The default cache size makes the Icache and Dcache "just a bit" too big to
fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
Manual (pages 36 and 37).

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : lm32_include.v
philpem@0 19 // Title : CPU global macros
philpem@0 20 // Version : 6.1.17
philpem@0 21 // : Initial Release
philpem@0 22 // Version : 7.0SP2, 3.0
philpem@0 23 // : No Change
philpem@0 24 // Version : 3.1
philpem@0 25 // : No Change
philpem@0 26 // Version : 3.2
philpem@0 27 // : No Change
philpem@0 28 // Version : 3.3
philpem@0 29 // : Support for extended configuration register
philpem@0 30 // =============================================================================
philpem@0 31
philpem@0 32 `ifdef LM32_INCLUDE_V
philpem@0 33 `else
philpem@0 34 `define LM32_INCLUDE_V
philpem@0 35
philpem@1 36 // (config opts from http://www.reflextor.org/trac/a51/browser/fpga/main/cores/lm32/rtl/lm32_include.v?rev=20)
philpem@1 37 //
philpem@1 38 // Common configuration options
philpem@1 39 //
philpem@1 40
philpem@1 41 `define CFG_EBA_RESET 32'h0
philpem@1 42 `define CFG_DEBA_RESET 32'h0
philpem@1 43
philpem@1 44 `define CFG_PL_MULTIPLY_ENABLED
philpem@1 45 `define CFG_PL_BARREL_SHIFT_ENABLED
philpem@1 46 `define CFG_SIGN_EXTEND_ENABLED
philpem@1 47 `define CFG_MC_DIVIDE_ENABLED
philpem@1 48
philpem@4 49 // [found by Milkymist dev'rs]
philpem@4 50 // Bug in Xst:
philpem@4 51 // CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software)
philpem@4 52 // CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all
philpem@4 53 // Works 100% OK with expensive synthesizers.
philpem@6 54 `define CFG_ICACHE_ENABLED
philpem@6 55 `define CFG_ICACHE_ASSOCIATIVITY 1
philpem@1 56 `define CFG_ICACHE_SETS 512
philpem@6 57 `define CFG_ICACHE_BYTES_PER_LINE 4
philpem@1 58 `define CFG_ICACHE_BASE_ADDRESS 32'h0
philpem@6 59 `define CFG_ICACHE_LIMIT 32'h7FFF_FFFF
philpem@1 60
philpem@1 61 `define CFG_DCACHE_ENABLED
philpem@6 62 `define CFG_DCACHE_ASSOCIATIVITY 1
philpem@1 63 `define CFG_DCACHE_SETS 512
philpem@6 64 `define CFG_DCACHE_BYTES_PER_LINE 4
philpem@1 65 `define CFG_DCACHE_BASE_ADDRESS 32'h0
philpem@6 66 `define CFG_DCACHE_LIMIT 32'h0FFF_FFFF
philpem@6 67
philpem@1 68 //
philpem@1 69 // End of common configuration options
philpem@1 70 //
philpem@0 71
philpem@0 72 `ifdef TRUE
philpem@0 73 `else
philpem@0 74 `define TRUE 1'b1
philpem@0 75 `define FALSE 1'b0
philpem@0 76 `define TRUE_N 1'b0
philpem@0 77 `define FALSE_N 1'b1
philpem@0 78 `endif
philpem@0 79
philpem@0 80 // Wishbone configuration
philpem@0 81 `define CFG_IWB_ENABLED
philpem@0 82 `define CFG_DWB_ENABLED
philpem@0 83
philpem@0 84 // Data-path width
philpem@0 85 `define LM32_WORD_WIDTH 32
philpem@0 86 `define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
philpem@0 87 `define LM32_SHIFT_WIDTH 5
philpem@0 88 `define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
philpem@0 89 `define LM32_BYTE_SELECT_WIDTH 4
philpem@0 90 `define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
philpem@0 91
philpem@0 92 // Register file size
philpem@0 93 `define LM32_REGISTERS 32
philpem@0 94 `define LM32_REG_IDX_WIDTH 5
philpem@0 95 `define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
philpem@0 96
philpem@0 97 // Standard register numbers
philpem@0 98 `define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
philpem@0 99 `define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
philpem@0 100 `define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
philpem@0 101
philpem@0 102 // Range of Program Counter. Two LSBs are always 0.
philpem@0 103 // `ifdef CFG_ICACHE_ENABLED
philpem@0 104 // `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
philpem@0 105 // `else
philpem@0 106 // `ifdef CFG_IWB_ENABLED
philpem@0 107 `define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
philpem@0 108 // `else
philpem@0 109 // `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH
philpem@0 110 // `endif
philpem@0 111 // `endif
philpem@0 112 `define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
philpem@0 113
philpem@0 114 // Range of an instruction
philpem@0 115 `define LM32_INSTRUCTION_WIDTH 32
philpem@0 116 `define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
philpem@0 117
philpem@0 118 // Adder operation
philpem@0 119 `define LM32_ADDER_OP_ADD 1'b0
philpem@0 120 `define LM32_ADDER_OP_SUBTRACT 1'b1
philpem@0 121
philpem@0 122 // Shift direction
philpem@0 123 `define LM32_SHIFT_OP_RIGHT 1'b0
philpem@0 124 `define LM32_SHIFT_OP_LEFT 1'b1
philpem@0 125
philpem@0 126 // Currently always enabled
philpem@0 127 `define CFG_BUS_ERRORS_ENABLED
philpem@0 128
philpem@0 129 // Derive macro that indicates whether we have single-stepping or not
philpem@0 130 `ifdef CFG_ROM_DEBUG_ENABLED
philpem@0 131 `define LM32_SINGLE_STEP_ENABLED
philpem@0 132 `else
philpem@0 133 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 134 `define LM32_SINGLE_STEP_ENABLED
philpem@0 135 `endif
philpem@0 136 `endif
philpem@0 137
philpem@0 138 // Derive macro that indicates whether JTAG interface is required
philpem@0 139 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 140 `define LM32_JTAG_ENABLED
philpem@0 141 `else
philpem@0 142 `ifdef CFG_DEBUG_ENABLED
philpem@0 143 `define LM32_JTAG_ENABLED
philpem@0 144 `else
philpem@0 145 `endif
philpem@0 146 `endif
philpem@0 147
philpem@0 148 // Derive macro that indicates whether we have a barrel-shifter or not
philpem@0 149 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
philpem@0 150 `define LM32_BARREL_SHIFT_ENABLED
philpem@0 151 `else // CFG_PL_BARREL_SHIFT_ENABLED
philpem@0 152 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
philpem@0 153 `define LM32_BARREL_SHIFT_ENABLED
philpem@0 154 `else
philpem@0 155 `define LM32_NO_BARREL_SHIFT
philpem@0 156 `endif
philpem@0 157 `endif // CFG_PL_BARREL_SHIFT_ENABLED
philpem@0 158
philpem@0 159 // Derive macro that indicates whether we have a multiplier or not
philpem@0 160 `ifdef CFG_PL_MULTIPLY_ENABLED
philpem@0 161 `define LM32_MULTIPLY_ENABLED
philpem@0 162 `else
philpem@0 163 `ifdef CFG_MC_MULTIPLY_ENABLED
philpem@0 164 `define LM32_MULTIPLY_ENABLED
philpem@0 165 `endif
philpem@0 166 `endif
philpem@0 167
philpem@0 168 // Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
philpem@0 169 `ifdef CFG_MC_DIVIDE_ENABLED
philpem@0 170 `define LM32_MC_ARITHMETIC_ENABLED
philpem@0 171 `endif
philpem@0 172 `ifdef CFG_MC_MULTIPLY_ENABLED
philpem@0 173 `define LM32_MC_ARITHMETIC_ENABLED
philpem@0 174 `endif
philpem@0 175 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
philpem@0 176 `define LM32_MC_ARITHMETIC_ENABLED
philpem@0 177 `endif
philpem@0 178
philpem@0 179 // Derive macro that indicates if we are using an EBR register file
philpem@0 180 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
philpem@0 181 `define LM32_EBR_REGISTER_FILE
philpem@0 182 `endif
philpem@0 183 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
philpem@0 184 `define LM32_EBR_REGISTER_FILE
philpem@0 185 `endif
philpem@0 186
philpem@0 187 // Revision number
philpem@0 188 `define LM32_REVISION 6'h02
philpem@0 189
philpem@0 190 // Logical operations - Function encoded directly in instruction
philpem@0 191 `define LM32_LOGIC_OP_RNG 3:0
philpem@0 192
philpem@0 193 // Conditions for conditional branches
philpem@0 194 `define LM32_CONDITION_WIDTH 3
philpem@0 195 `define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
philpem@0 196 `define LM32_CONDITION_E 3'b001
philpem@0 197 `define LM32_CONDITION_G 3'b010
philpem@0 198 `define LM32_CONDITION_GE 3'b011
philpem@0 199 `define LM32_CONDITION_GEU 3'b100
philpem@0 200 `define LM32_CONDITION_GU 3'b101
philpem@0 201 `define LM32_CONDITION_NE 3'b111
philpem@0 202 `define LM32_CONDITION_U1 3'b000
philpem@0 203 `define LM32_CONDITION_U2 3'b110
philpem@0 204
philpem@0 205 // Size of load or store instruction - Encoding corresponds to opcode
philpem@0 206 `define LM32_SIZE_WIDTH 2
philpem@0 207 `define LM32_SIZE_RNG 1:0
philpem@0 208 `define LM32_SIZE_BYTE 2'b00
philpem@0 209 `define LM32_SIZE_HWORD 2'b11
philpem@0 210 `define LM32_SIZE_WORD 2'b10
philpem@0 211 `define LM32_ADDRESS_LSBS_WIDTH 2
philpem@0 212
philpem@0 213 // Width and range of a CSR index
philpem@0 214 `ifdef CFG_DEBUG_ENABLED
philpem@0 215 `define LM32_CSR_WIDTH 5
philpem@0 216 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
philpem@0 217 `else
philpem@0 218 `ifdef CFG_JTAG_ENABLED
philpem@0 219 `define LM32_CSR_WIDTH 4
philpem@0 220 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
philpem@0 221 `else
philpem@0 222 `define LM32_CSR_WIDTH 3
philpem@0 223 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
philpem@0 224 `endif
philpem@0 225 `endif
philpem@0 226
philpem@0 227 // CSR indices
philpem@0 228 `define LM32_CSR_IE `LM32_CSR_WIDTH'h0
philpem@0 229 `define LM32_CSR_IM `LM32_CSR_WIDTH'h1
philpem@0 230 `define LM32_CSR_IP `LM32_CSR_WIDTH'h2
philpem@0 231 `define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
philpem@0 232 `define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
philpem@0 233 `define LM32_CSR_CC `LM32_CSR_WIDTH'h5
philpem@0 234 `define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
philpem@0 235 `define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
philpem@0 236 `ifdef CFG_DEBUG_ENABLED
philpem@0 237 `define LM32_CSR_DC `LM32_CSR_WIDTH'h8
philpem@0 238 `define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
philpem@0 239 `endif
philpem@0 240 `define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha
philpem@0 241 `ifdef CFG_JTAG_ENABLED
philpem@0 242 `define LM32_CSR_JTX `LM32_CSR_WIDTH'he
philpem@0 243 `define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
philpem@0 244 `endif
philpem@0 245 `ifdef CFG_DEBUG_ENABLED
philpem@0 246 `define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
philpem@0 247 `define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
philpem@0 248 `define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
philpem@0 249 `define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
philpem@0 250 `define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
philpem@0 251 `define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
philpem@0 252 `define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
philpem@0 253 `define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
philpem@0 254 `endif
philpem@0 255
philpem@0 256 // Values for WPC CSR
philpem@0 257 `define LM32_WPC_C_RNG 1:0
philpem@0 258 `define LM32_WPC_C_DISABLED 2'b00
philpem@0 259 `define LM32_WPC_C_READ 2'b01
philpem@0 260 `define LM32_WPC_C_WRITE 2'b10
philpem@0 261 `define LM32_WPC_C_READ_WRITE 2'b11
philpem@0 262
philpem@0 263 // Exception IDs
philpem@0 264 `define LM32_EID_WIDTH 3
philpem@0 265 `define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
philpem@0 266 `define LM32_EID_RESET 3'h0
philpem@0 267 `define LM32_EID_BREAKPOINT 3'd1
philpem@0 268 `define LM32_EID_INST_BUS_ERROR 3'h2
philpem@0 269 `define LM32_EID_WATCHPOINT 3'd3
philpem@0 270 `define LM32_EID_DATA_BUS_ERROR 3'h4
philpem@0 271 `define LM32_EID_DIVIDE_BY_ZERO 3'h5
philpem@0 272 `define LM32_EID_INTERRUPT 3'h6
philpem@0 273 `define LM32_EID_SCALL 3'h7
philpem@0 274
philpem@0 275 // Pipeline result selection mux controls
philpem@0 276
philpem@0 277 `define LM32_D_RESULT_SEL_0_RNG 0:0
philpem@0 278 `define LM32_D_RESULT_SEL_0_REG_0 1'b0
philpem@0 279 `define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
philpem@0 280
philpem@0 281 `define LM32_D_RESULT_SEL_1_RNG 1:0
philpem@0 282 `define LM32_D_RESULT_SEL_1_ZERO 2'b00
philpem@0 283 `define LM32_D_RESULT_SEL_1_REG_1 2'b01
philpem@0 284 `define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
philpem@0 285
philpem@0 286 `define LM32_USER_OPCODE_WIDTH 11
philpem@0 287 `define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
philpem@0 288
philpem@0 289 // Derive a macro to indicate if either of the caches are implemented
philpem@0 290 `ifdef CFG_ICACHE_ENABLED
philpem@0 291 `define LM32_CACHE_ENABLED
philpem@0 292 `else
philpem@0 293 `ifdef CFG_DCACHE_ENABLED
philpem@0 294 `define LM32_CACHE_ENABLED
philpem@0 295 `endif
philpem@0 296 `endif
philpem@0 297
philpem@0 298 /////////////////////////////////////////////////////
philpem@0 299 // Interrupts
philpem@0 300 /////////////////////////////////////////////////////
philpem@0 301
philpem@0 302 // Always enable interrupts
philpem@0 303 `define CFG_INTERRUPTS_ENABLED
philpem@0 304
philpem@0 305 // Currently this is fixed to 32 and should not be changed
philpem@0 306 `define CFG_INTERRUPTS 32
philpem@0 307 `define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
philpem@0 308 `define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
philpem@0 309
philpem@0 310 /////////////////////////////////////////////////////
philpem@0 311 // General
philpem@0 312 /////////////////////////////////////////////////////
philpem@0 313
philpem@0 314 // Sub-word range types
philpem@0 315 `define LM32_BYTE_WIDTH 8
philpem@0 316 `define LM32_BYTE_RNG 7:0
philpem@0 317 `define LM32_HWORD_WIDTH 16
philpem@0 318 `define LM32_HWORD_RNG 15:0
philpem@0 319
philpem@0 320 // Word sub-byte indicies
philpem@0 321 `define LM32_BYTE_0_RNG 7:0
philpem@0 322 `define LM32_BYTE_1_RNG 15:8
philpem@0 323 `define LM32_BYTE_2_RNG 23:16
philpem@0 324 `define LM32_BYTE_3_RNG 31:24
philpem@0 325
philpem@0 326 // Word sub-halfword indices
philpem@0 327 `define LM32_HWORD_0_RNG 15:0
philpem@0 328 `define LM32_HWORD_1_RNG 31:16
philpem@0 329
philpem@0 330 // Use an asynchronous reset
philpem@0 331 // To use a synchronous reset, define this macro as nothing
philpem@0 332 `define CFG_RESET_SENSITIVITY
philpem@0 333
philpem@0 334 // V.T. Srce
philpem@0 335 `define SRCE
philpem@0 336
philpem@0 337 // Whether to include context registers for debug exceptions
philpem@0 338 // in addition to standard exception handling registers
philpem@0 339 // Bizarre - Removing this increases LUT count!
philpem@0 340 `define CFG_DEBUG_EXCEPTIONS_ENABLED
philpem@0 341
philpem@0 342 // Wishbone defines
philpem@0 343 // Refer to Wishbone System-on-Chip Interconnection Architecture
philpem@0 344 // These should probably be moved to a Wishbone common file
philpem@0 345
philpem@0 346 // Wishbone cycle types
philpem@0 347 `define LM32_CTYPE_WIDTH 3
philpem@0 348 `define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
philpem@0 349 `define LM32_CTYPE_CLASSIC 3'b000
philpem@0 350 `define LM32_CTYPE_CONSTANT 3'b001
philpem@0 351 `define LM32_CTYPE_INCREMENTING 3'b010
philpem@0 352 `define LM32_CTYPE_END 3'b111
philpem@0 353
philpem@0 354 // Wishbone burst types
philpem@0 355 `define LM32_BTYPE_WIDTH 2
philpem@0 356 `define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
philpem@0 357 `define LM32_BTYPE_LINEAR 2'b00
philpem@0 358 `define LM32_BTYPE_4_BEAT 2'b01
philpem@0 359 `define LM32_BTYPE_8_BEAT 2'b10
philpem@0 360 `define LM32_BTYPE_16_BEAT 2'b11
philpem@0 361
philpem@0 362 `endif