jtag_lm32.v

Sun, 04 Apr 2010 22:05:07 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 04 Apr 2010 22:05:07 +0100
changeset 3
b153470d41c5
parent 0
cd0b58aa6f83
child 26
73de224304c1
permissions
-rw-r--r--

remove more Lattice-specific fluff

Code now synthesizes properly on Altera Quartus 9.0 build 235

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : jtag_lm32.v
philpem@0 19 // Title : JTAG data register for LM32 CPU debug interface
philpem@0 20 // Version : 6.0.13
philpem@0 21 // : Initial Release
philpem@0 22 // Version : 7.0SP2, 3.0
philpem@0 23 // : No Change
philpem@0 24 // Version : 3.1
philpem@0 25 // : No Change
philpem@0 26 // =============================================================================
philpem@0 27
philpem@0 28 /////////////////////////////////////////////////////
philpem@0 29 // Module interface
philpem@0 30 /////////////////////////////////////////////////////
philpem@0 31
philpem@0 32 module jtag_lm32 (
philpem@0 33 input JTCK,
philpem@0 34 input JTDI,
philpem@0 35 output JTDO2,
philpem@0 36 input JSHIFT,
philpem@0 37 input JUPDATE,
philpem@0 38 input JRSTN,
philpem@0 39 input JCE2,
philpem@0 40 input JTAGREG_ENABLE,
philpem@0 41 input CONTROL_DATAN,
philpem@0 42 output REG_UPDATE,
philpem@0 43 input [7:0] REG_D,
philpem@0 44 input [2:0] REG_ADDR_D,
philpem@0 45 output [7:0] REG_Q,
philpem@0 46 output [2:0] REG_ADDR_Q
philpem@0 47 );
philpem@0 48
philpem@0 49 /////////////////////////////////////////////////////
philpem@0 50 // Internal nets and registers
philpem@0 51 /////////////////////////////////////////////////////
philpem@0 52
philpem@0 53 wire [9:0] tdibus;
philpem@0 54
philpem@0 55 /////////////////////////////////////////////////////
philpem@0 56 // Instantiations
philpem@0 57 /////////////////////////////////////////////////////
philpem@0 58
philpem@0 59 TYPEA DATA_BIT0 (
philpem@0 60 .CLK(JTCK),
philpem@0 61 .RESET_N(JRSTN),
philpem@0 62 .CLKEN(clk_enable),
philpem@0 63 .TDI(JTDI),
philpem@0 64 .TDO(tdibus[0]),
philpem@0 65 .DATA_OUT(REG_Q[0]),
philpem@0 66 .DATA_IN(REG_D[0]),
philpem@0 67 .CAPTURE_DR(captureDr),
philpem@0 68 .UPDATE_DR(JUPDATE)
philpem@0 69 );
philpem@0 70
philpem@0 71 TYPEA DATA_BIT1 (
philpem@0 72 .CLK(JTCK),
philpem@0 73 .RESET_N(JRSTN),
philpem@0 74 .CLKEN(clk_enable),
philpem@0 75 .TDI(tdibus[0]),
philpem@0 76 .TDO(tdibus[1]),
philpem@0 77 .DATA_OUT(REG_Q[1]),
philpem@0 78 .DATA_IN(REG_D[1]),
philpem@0 79 .CAPTURE_DR(captureDr),
philpem@0 80 .UPDATE_DR(JUPDATE)
philpem@0 81 );
philpem@0 82
philpem@0 83 TYPEA DATA_BIT2 (
philpem@0 84 .CLK(JTCK),
philpem@0 85 .RESET_N(JRSTN),
philpem@0 86 .CLKEN(clk_enable),
philpem@0 87 .TDI(tdibus[1]),
philpem@0 88 .TDO(tdibus[2]),
philpem@0 89 .DATA_OUT(REG_Q[2]),
philpem@0 90 .DATA_IN(REG_D[2]),
philpem@0 91 .CAPTURE_DR(captureDr),
philpem@0 92 .UPDATE_DR(JUPDATE)
philpem@0 93 );
philpem@0 94
philpem@0 95 TYPEA DATA_BIT3 (
philpem@0 96 .CLK(JTCK),
philpem@0 97 .RESET_N(JRSTN),
philpem@0 98 .CLKEN(clk_enable),
philpem@0 99 .TDI(tdibus[2]),
philpem@0 100 .TDO(tdibus[3]),
philpem@0 101 .DATA_OUT(REG_Q[3]),
philpem@0 102 .DATA_IN(REG_D[3]),
philpem@0 103 .CAPTURE_DR(captureDr),
philpem@0 104 .UPDATE_DR(JUPDATE)
philpem@0 105 );
philpem@0 106
philpem@0 107 TYPEA DATA_BIT4 (
philpem@0 108 .CLK(JTCK),
philpem@0 109 .RESET_N(JRSTN),
philpem@0 110 .CLKEN(clk_enable),
philpem@0 111 .TDI(tdibus[3]),
philpem@0 112 .TDO(tdibus[4]),
philpem@0 113 .DATA_OUT(REG_Q[4]),
philpem@0 114 .DATA_IN(REG_D[4]),
philpem@0 115 .CAPTURE_DR(captureDr),
philpem@0 116 .UPDATE_DR(JUPDATE)
philpem@0 117 );
philpem@0 118
philpem@0 119 TYPEA DATA_BIT5 (
philpem@0 120 .CLK(JTCK),
philpem@0 121 .RESET_N(JRSTN),
philpem@0 122 .CLKEN(clk_enable),
philpem@0 123 .TDI(tdibus[4]),
philpem@0 124 .TDO(tdibus[5]),
philpem@0 125 .DATA_OUT(REG_Q[5]),
philpem@0 126 .DATA_IN(REG_D[5]),
philpem@0 127 .CAPTURE_DR(captureDr),
philpem@0 128 .UPDATE_DR(JUPDATE)
philpem@0 129 );
philpem@0 130
philpem@0 131 TYPEA DATA_BIT6 (
philpem@0 132 .CLK(JTCK),
philpem@0 133 .RESET_N(JRSTN),
philpem@0 134 .CLKEN(clk_enable),
philpem@0 135 .TDI(tdibus[5]),
philpem@0 136 .TDO(tdibus[6]),
philpem@0 137 .DATA_OUT(REG_Q[6]),
philpem@0 138 .DATA_IN(REG_D[6]),
philpem@0 139 .CAPTURE_DR(captureDr),
philpem@0 140 .UPDATE_DR(JUPDATE)
philpem@0 141 );
philpem@0 142
philpem@0 143 TYPEA DATA_BIT7 (
philpem@0 144 .CLK(JTCK),
philpem@0 145 .RESET_N(JRSTN),
philpem@0 146 .CLKEN(clk_enable),
philpem@0 147 .TDI(tdibus[6]),
philpem@0 148 .TDO(tdibus[7]),
philpem@0 149 .DATA_OUT(REG_Q[7]),
philpem@0 150 .DATA_IN(REG_D[7]),
philpem@0 151 .CAPTURE_DR(captureDr),
philpem@0 152 .UPDATE_DR(JUPDATE)
philpem@0 153 );
philpem@0 154
philpem@0 155 TYPEA ADDR_BIT0 (
philpem@0 156 .CLK(JTCK),
philpem@0 157 .RESET_N(JRSTN),
philpem@0 158 .CLKEN(clk_enable),
philpem@0 159 .TDI(tdibus[7]),
philpem@0 160 .TDO(tdibus[8]),
philpem@0 161 .DATA_OUT(REG_ADDR_Q[0]),
philpem@0 162 .DATA_IN(REG_ADDR_D[0]),
philpem@0 163 .CAPTURE_DR(captureDr),
philpem@0 164 .UPDATE_DR(JUPDATE)
philpem@0 165 );
philpem@0 166
philpem@0 167 TYPEA ADDR_BIT1 (
philpem@0 168 .CLK(JTCK),
philpem@0 169 .RESET_N(JRSTN),
philpem@0 170 .CLKEN(clk_enable),
philpem@0 171 .TDI(tdibus[8]),
philpem@0 172 .TDO(tdibus[9]),
philpem@0 173 .DATA_OUT(REG_ADDR_Q[1]),
philpem@0 174 .DATA_IN(REG_ADDR_D[1]),
philpem@0 175 .CAPTURE_DR(captureDr),
philpem@0 176 .UPDATE_DR(JUPDATE)
philpem@0 177 );
philpem@0 178
philpem@0 179 TYPEA ADDR_BIT2 (
philpem@0 180 .CLK(JTCK),
philpem@0 181 .RESET_N(JRSTN),
philpem@0 182 .CLKEN(clk_enable),
philpem@0 183 .TDI(tdibus[9]),
philpem@0 184 .TDO(JTDO2),
philpem@0 185 .DATA_OUT(REG_ADDR_Q[2]),
philpem@0 186 .DATA_IN(REG_ADDR_D[2]),
philpem@0 187 .CAPTURE_DR(captureDr),
philpem@0 188 .UPDATE_DR(JUPDATE)
philpem@0 189 );
philpem@0 190
philpem@0 191 /////////////////////////////////////////////////////
philpem@0 192 // Combinational logic
philpem@0 193 /////////////////////////////////////////////////////
philpem@0 194
philpem@0 195 assign clk_enable = JTAGREG_ENABLE & JCE2;
philpem@0 196 assign captureDr = !JSHIFT & JCE2;
philpem@0 197 // JCE2 is only active during shift
philpem@0 198 assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
philpem@0 199
philpem@0 200 endmodule