jtag_cores.v

Sun, 06 Mar 2011 21:03:32 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:03:32 +0000
changeset 18
cc945f778cd7
parent 17
50bf3061dbff
permissions
-rwxr-xr-x

Commit GSI patches from Wesley Terpstra

- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC

Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?

Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>

philpem@18 1 // Modified by GSI to use simple positive edge clocking and the JTAG capture state
philpem@18 2
philpem@16 3 module jtag_cores (
philpem@16 4 input [7:0] reg_d,
philpem@16 5 input [2:0] reg_addr_d,
philpem@16 6 output reg_update,
philpem@16 7 output [7:0] reg_q,
philpem@16 8 output [2:0] reg_addr_q,
philpem@16 9 output jtck,
philpem@16 10 output jrstn
philpem@16 11 );
philpem@0 12
philpem@16 13 wire tck;
philpem@16 14 wire tdi;
philpem@16 15 wire tdo;
philpem@18 16 wire capture;
philpem@16 17 wire shift;
philpem@16 18 wire update;
philpem@18 19 wire e1dr;
philpem@16 20 wire reset;
philpem@16 21
philpem@16 22 jtag_tap jtag_tap (
philpem@16 23 .tck(tck),
philpem@16 24 .tdi(tdi),
philpem@16 25 .tdo(tdo),
philpem@18 26 .capture(capture),
philpem@16 27 .shift(shift),
philpem@18 28 .e1dr(e1dr),
philpem@16 29 .update(update),
philpem@16 30 .reset(reset)
philpem@14 31 );
philpem@0 32
philpem@16 33 reg [10:0] jtag_shift;
philpem@16 34 reg [10:0] jtag_latched;
philpem@0 35
philpem@18 36 always @(posedge tck)
philpem@16 37 begin
philpem@16 38 if(reset)
philpem@16 39 jtag_shift <= 11'b0;
philpem@16 40 else begin
philpem@18 41 if (shift)
philpem@16 42 jtag_shift <= {tdi, jtag_shift[10:1]};
philpem@18 43 else if (capture)
philpem@16 44 jtag_shift <= {reg_d, reg_addr_d};
philpem@16 45 end
philpem@16 46 end
philpem@0 47
philpem@16 48 assign tdo = jtag_shift[0];
philpem@0 49
philpem@18 50 always @(posedge tck)
philpem@16 51 begin
philpem@16 52 if(reset)
philpem@16 53 jtag_latched <= 11'b0;
philpem@18 54 else begin
philpem@18 55 if (e1dr)
philpem@18 56 jtag_latched <= jtag_shift;
philpem@18 57 end
philpem@16 58 end
philpem@16 59
philpem@17 60 assign reg_update = update;
philpem@16 61 assign reg_q = jtag_latched[10:3];
philpem@16 62 assign reg_addr_q = jtag_latched[2:0];
philpem@16 63 assign jtck = tck;
philpem@16 64 assign jrstn = ~reset;
philpem@16 65
philpem@0 66 endmodule