Sun, 06 Mar 2011 21:03:32 +0000
Commit GSI patches from Wesley Terpstra
- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC
Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?
Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>
| philpem@18 | 1 | module jtag_tap( |
| philpem@18 | 2 | output tck, |
| philpem@18 | 3 | output tdi, |
| philpem@18 | 4 | input tdo, |
| philpem@18 | 5 | output capture, |
| philpem@18 | 6 | output shift, |
| philpem@18 | 7 | output e1dr, |
| philpem@18 | 8 | output update, |
| philpem@18 | 9 | output reset |
| philpem@18 | 10 | ); |
| philpem@18 | 11 | |
| philpem@18 | 12 | assign reset = 0; |
| philpem@18 | 13 | wire nil1, nil2, nil3, nil4; |
| philpem@18 | 14 | |
| philpem@18 | 15 | sld_virtual_jtag altera_jtag( |
| philpem@18 | 16 | .ir_in (), |
| philpem@18 | 17 | .ir_out (), |
| philpem@18 | 18 | .tck (tck), |
| philpem@18 | 19 | .tdo (tdo), |
| philpem@18 | 20 | .tdi (tdi), |
| philpem@18 | 21 | .virtual_state_cdr (capture), |
| philpem@18 | 22 | .virtual_state_sdr (shift), |
| philpem@18 | 23 | .virtual_state_e1dr (e1dr), |
| philpem@18 | 24 | .virtual_state_pdr (nil1), |
| philpem@18 | 25 | .virtual_state_e2dr (nil2), |
| philpem@18 | 26 | .virtual_state_udr (update), |
| philpem@18 | 27 | .virtual_state_cir (nil3), |
| philpem@18 | 28 | .virtual_state_uir (nil4) |
| philpem@18 | 29 | // synopsys translate_off |
| philpem@18 | 30 | , |
| philpem@18 | 31 | .jtag_state_cdr (), |
| philpem@18 | 32 | .jtag_state_cir (), |
| philpem@18 | 33 | .jtag_state_e1dr (), |
| philpem@18 | 34 | .jtag_state_e1ir (), |
| philpem@18 | 35 | .jtag_state_e2dr (), |
| philpem@18 | 36 | .jtag_state_e2ir (), |
| philpem@18 | 37 | .jtag_state_pdr (), |
| philpem@18 | 38 | .jtag_state_pir (), |
| philpem@18 | 39 | .jtag_state_rti (), |
| philpem@18 | 40 | .jtag_state_sdr (), |
| philpem@18 | 41 | .jtag_state_sdrs (), |
| philpem@18 | 42 | .jtag_state_sir (), |
| philpem@18 | 43 | .jtag_state_sirs (), |
| philpem@18 | 44 | .jtag_state_tlr (), |
| philpem@18 | 45 | .jtag_state_udr (), |
| philpem@18 | 46 | .jtag_state_uir (), |
| philpem@18 | 47 | .tms () |
| philpem@18 | 48 | // synopsys translate_on |
| philpem@18 | 49 | ); |
| philpem@18 | 50 | |
| philpem@18 | 51 | defparam |
| philpem@18 | 52 | altera_jtag.sld_auto_instance_index = "YES", |
| philpem@18 | 53 | altera_jtag.sld_instance_index = 0, |
| philpem@18 | 54 | altera_jtag.sld_ir_width = 1, |
| philpem@18 | 55 | altera_jtag.sld_sim_action = "", |
| philpem@18 | 56 | altera_jtag.sld_sim_n_scan = 0, |
| philpem@18 | 57 | altera_jtag.sld_sim_total_length = 0; |
| philpem@18 | 58 | |
| philpem@18 | 59 | endmodule |