lm32_jtag.v

Sun, 06 Mar 2011 21:03:32 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:03:32 +0000
changeset 18
cc945f778cd7
parent 14
54dd95f89113
permissions
-rwxr-xr-x

Commit GSI patches from Wesley Terpstra

- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC

Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?

Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : lm32_jtag.v
philpem@0 19 // Title : JTAG interface
philpem@0 20 // Dependencies : lm32_include.v
philpem@0 21 // Version : 6.1.17
philpem@0 22 // : Initial Release
philpem@0 23 // Version : 7.0SP2, 3.0
philpem@0 24 // : No Change
philpem@0 25 // Version : 3.1
philpem@0 26 // : No Change
philpem@0 27 // =============================================================================
philpem@0 28
philpem@0 29 `include "lm32_include.v"
philpem@0 30
philpem@0 31 `ifdef CFG_JTAG_ENABLED
philpem@0 32
philpem@0 33 `define LM32_DP 3'b000
philpem@0 34 `define LM32_TX 3'b001
philpem@0 35 `define LM32_RX 3'b010
philpem@0 36
philpem@0 37 // LM32 Debug Protocol commands IDs
philpem@0 38 `define LM32_DP_RNG 3:0
philpem@0 39 `define LM32_DP_READ_MEMORY 4'b0001
philpem@0 40 `define LM32_DP_WRITE_MEMORY 4'b0010
philpem@0 41 `define LM32_DP_READ_SEQUENTIAL 4'b0011
philpem@0 42 `define LM32_DP_WRITE_SEQUENTIAL 4'b0100
philpem@0 43 `define LM32_DP_WRITE_CSR 4'b0101
philpem@0 44 `define LM32_DP_BREAK 4'b0110
philpem@0 45 `define LM32_DP_RESET 4'b0111
philpem@0 46
philpem@0 47 // States for FSM
philpem@0 48 `define LM32_JTAG_STATE_RNG 3:0
philpem@0 49 `define LM32_JTAG_STATE_READ_COMMAND 4'h0
philpem@0 50 `define LM32_JTAG_STATE_READ_BYTE_0 4'h1
philpem@0 51 `define LM32_JTAG_STATE_READ_BYTE_1 4'h2
philpem@0 52 `define LM32_JTAG_STATE_READ_BYTE_2 4'h3
philpem@0 53 `define LM32_JTAG_STATE_READ_BYTE_3 4'h4
philpem@0 54 `define LM32_JTAG_STATE_READ_BYTE_4 4'h5
philpem@0 55 `define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
philpem@0 56 `define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
philpem@0 57 `define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
philpem@0 58
philpem@0 59 /////////////////////////////////////////////////////
philpem@0 60 // Module interface
philpem@0 61 /////////////////////////////////////////////////////
philpem@0 62
philpem@0 63 module lm32_jtag (
philpem@0 64 // ----- Inputs -------
philpem@0 65 clk_i,
philpem@0 66 rst_i,
philpem@0 67 jtag_clk,
philpem@0 68 jtag_update,
philpem@0 69 jtag_reg_q,
philpem@0 70 jtag_reg_addr_q,
philpem@0 71 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 72 csr,
philpem@0 73 csr_write_enable,
philpem@0 74 csr_write_data,
philpem@0 75 stall_x,
philpem@0 76 `endif
philpem@0 77 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 78 jtag_read_data,
philpem@0 79 jtag_access_complete,
philpem@0 80 `endif
philpem@0 81 `ifdef CFG_DEBUG_ENABLED
philpem@0 82 exception_q_w,
philpem@0 83 `endif
philpem@0 84 // ----- Outputs -------
philpem@0 85 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 86 jtx_csr_read_data,
philpem@0 87 jrx_csr_read_data,
philpem@0 88 `endif
philpem@0 89 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 90 jtag_csr_write_enable,
philpem@0 91 jtag_csr_write_data,
philpem@0 92 jtag_csr,
philpem@0 93 jtag_read_enable,
philpem@0 94 jtag_write_enable,
philpem@0 95 jtag_write_data,
philpem@0 96 jtag_address,
philpem@0 97 `endif
philpem@0 98 `ifdef CFG_DEBUG_ENABLED
philpem@0 99 jtag_break,
philpem@0 100 jtag_reset,
philpem@0 101 `endif
philpem@0 102 jtag_reg_d,
philpem@0 103 jtag_reg_addr_d
philpem@0 104 );
philpem@0 105
philpem@0 106 /////////////////////////////////////////////////////
philpem@0 107 // Inputs
philpem@0 108 /////////////////////////////////////////////////////
philpem@0 109
philpem@0 110 input clk_i; // Clock
philpem@0 111 input rst_i; // Reset
philpem@0 112
philpem@0 113 input jtag_clk; // JTAG clock
philpem@0 114 input jtag_update; // JTAG data register has been updated
philpem@0 115 input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
philpem@0 116 input [2:0] jtag_reg_addr_q; // JTAG data register
philpem@0 117
philpem@0 118 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 119 input [`LM32_CSR_RNG] csr; // CSR to write
philpem@0 120 input csr_write_enable; // CSR write enable
philpem@0 121 input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
philpem@0 122 input stall_x; // Stall instruction in X stage
philpem@0 123 `endif
philpem@0 124 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 125 input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
philpem@0 126 input jtag_access_complete; // Memory access if complete
philpem@0 127 `endif
philpem@0 128 `ifdef CFG_DEBUG_ENABLED
philpem@0 129 input exception_q_w; // Indicates an exception has occured in W stage
philpem@0 130 `endif
philpem@0 131
philpem@0 132 /////////////////////////////////////////////////////
philpem@0 133 // Outputs
philpem@0 134 /////////////////////////////////////////////////////
philpem@0 135
philpem@0 136 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 137 output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
philpem@0 138 wire [`LM32_WORD_RNG] jtx_csr_read_data;
philpem@0 139 output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
philpem@0 140 wire [`LM32_WORD_RNG] jrx_csr_read_data;
philpem@0 141 `endif
philpem@0 142 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 143 output jtag_csr_write_enable; // CSR write enable
philpem@0 144 reg jtag_csr_write_enable;
philpem@0 145 output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
philpem@0 146 wire [`LM32_WORD_RNG] jtag_csr_write_data;
philpem@0 147 output [`LM32_CSR_RNG] jtag_csr; // CSR to write
philpem@0 148 wire [`LM32_CSR_RNG] jtag_csr;
philpem@0 149 output jtag_read_enable; // Memory read enable
philpem@0 150 reg jtag_read_enable;
philpem@0 151 output jtag_write_enable; // Memory write enable
philpem@0 152 reg jtag_write_enable;
philpem@0 153 output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
philpem@0 154 wire [`LM32_BYTE_RNG] jtag_write_data;
philpem@0 155 output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
philpem@0 156 wire [`LM32_WORD_RNG] jtag_address;
philpem@0 157 `endif
philpem@0 158 `ifdef CFG_DEBUG_ENABLED
philpem@0 159 output jtag_break; // Request to raise a breakpoint exception
philpem@0 160 reg jtag_break;
philpem@0 161 output jtag_reset; // Request to raise a reset exception
philpem@0 162 reg jtag_reset;
philpem@0 163 `endif
philpem@0 164 output [`LM32_BYTE_RNG] jtag_reg_d;
philpem@0 165 reg [`LM32_BYTE_RNG] jtag_reg_d;
philpem@0 166 output [2:0] jtag_reg_addr_d;
philpem@0 167 wire [2:0] jtag_reg_addr_d;
philpem@0 168
philpem@0 169 /////////////////////////////////////////////////////
philpem@0 170 // Internal nets and registers
philpem@0 171 /////////////////////////////////////////////////////
philpem@0 172
philpem@18 173 reg rx_update; // Clock-domain crossing registers
philpem@18 174 reg rx_update_r; // Registered version of rx_update
philpem@18 175 reg rx_update_r_r; // Registered version of rx_update_r
philpem@18 176 reg rx_update_r_r_r; // Registered version of rx_update_r_r
philpem@0 177
philpem@18 178 // These wires come from the JTAG clock domain.
philpem@18 179 // They have been held unchanged for an entire JTAG clock cycle before the jtag_update toggle flips
philpem@18 180 wire [`LM32_BYTE_RNG] rx_byte;
philpem@18 181 wire [2:0] rx_addr;
philpem@0 182
philpem@0 183 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 184 reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
philpem@0 185 reg uart_tx_valid; // TX data is valid
philpem@0 186 reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
philpem@0 187 reg uart_rx_valid; // RX data is valid
philpem@0 188 `endif
philpem@0 189
philpem@0 190 reg [`LM32_DP_RNG] command; // The last received command
philpem@0 191 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 192 reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
philpem@0 193 reg [`LM32_BYTE_RNG] jtag_byte_1;
philpem@0 194 reg [`LM32_BYTE_RNG] jtag_byte_2;
philpem@0 195 reg [`LM32_BYTE_RNG] jtag_byte_3;
philpem@0 196 reg [`LM32_BYTE_RNG] jtag_byte_4;
philpem@0 197 reg processing; // Indicates if we're still processing a memory read/write
philpem@0 198 `endif
philpem@0 199
philpem@0 200 reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
philpem@0 201
philpem@0 202 /////////////////////////////////////////////////////
philpem@0 203 // Combinational Logic
philpem@0 204 /////////////////////////////////////////////////////
philpem@0 205
philpem@0 206 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 207 assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
philpem@0 208 assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
philpem@0 209 assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
philpem@0 210 assign jtag_write_data = jtag_byte_4;
philpem@0 211 `endif
philpem@0 212
philpem@0 213 // Generate status flags for reading via the JTAG interface
philpem@0 214 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 215 assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
philpem@0 216 `else
philpem@0 217 assign jtag_reg_addr_d[1:0] = 2'b00;
philpem@0 218 `endif
philpem@0 219 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 220 assign jtag_reg_addr_d[2] = processing;
philpem@0 221 `else
philpem@0 222 assign jtag_reg_addr_d[2] = 1'b0;
philpem@0 223 `endif
philpem@0 224
philpem@0 225 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 226 assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
philpem@0 227 assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
philpem@0 228 `endif
philpem@0 229
philpem@0 230 /////////////////////////////////////////////////////
philpem@0 231 // Sequential Logic
philpem@0 232 /////////////////////////////////////////////////////
philpem@0 233
philpem@18 234 assign rx_byte = jtag_reg_q;
philpem@18 235 assign rx_addr = jtag_reg_addr_q;
philpem@0 236
philpem@18 237 // The JTAG latched jtag_reg[_addr]_q at least one JTCK before jtag_update is raised
philpem@18 238 // Thus, they are stable (and safe to sample) when jtag_update is high
philpem@0 239 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 240 begin
philpem@0 241 if (rst_i == `TRUE)
philpem@0 242 begin
philpem@18 243 rx_update <= 1'b0;
philpem@18 244 rx_update_r <= 1'b0;
philpem@18 245 rx_update_r_r <= 1'b0;
philpem@18 246 rx_update_r_r_r <= 1'b0;
philpem@0 247 end
philpem@0 248 else
philpem@0 249 begin
philpem@18 250 rx_update <= jtag_update;
philpem@18 251 rx_update_r <= rx_update;
philpem@18 252 rx_update_r_r <= rx_update_r;
philpem@18 253 rx_update_r_r_r <= rx_update_r_r;
philpem@0 254 end
philpem@0 255 end
philpem@0 256
philpem@0 257 // LM32 debug protocol state machine
philpem@0 258 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 259 begin
philpem@0 260 if (rst_i == `TRUE)
philpem@0 261 begin
philpem@0 262 state <= `LM32_JTAG_STATE_READ_COMMAND;
philpem@0 263 command <= 4'b0000;
philpem@0 264 jtag_reg_d <= 8'h00;
philpem@0 265 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 266 processing <= `FALSE;
philpem@0 267 jtag_csr_write_enable <= `FALSE;
philpem@0 268 jtag_read_enable <= `FALSE;
philpem@0 269 jtag_write_enable <= `FALSE;
philpem@0 270 `endif
philpem@0 271 `ifdef CFG_DEBUG_ENABLED
philpem@0 272 jtag_break <= `FALSE;
philpem@0 273 jtag_reset <= `FALSE;
philpem@0 274 `endif
philpem@0 275 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 276 uart_tx_byte <= 8'h00;
philpem@0 277 uart_tx_valid <= `FALSE;
philpem@0 278 uart_rx_byte <= 8'h00;
philpem@0 279 uart_rx_valid <= `FALSE;
philpem@0 280 `endif
philpem@0 281 end
philpem@0 282 else
philpem@0 283 begin
philpem@0 284 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 285 if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
philpem@0 286 begin
philpem@0 287 case (csr)
philpem@0 288 `LM32_CSR_JTX:
philpem@0 289 begin
philpem@0 290 // Set flag indicating data is available
philpem@0 291 uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
philpem@0 292 uart_tx_valid <= `TRUE;
philpem@0 293 end
philpem@0 294 `LM32_CSR_JRX:
philpem@0 295 begin
philpem@0 296 // Clear flag indidicating data has been received
philpem@0 297 uart_rx_valid <= `FALSE;
philpem@0 298 end
philpem@0 299 endcase
philpem@0 300 end
philpem@0 301 `endif
philpem@0 302 `ifdef CFG_DEBUG_ENABLED
philpem@0 303 // When an exception has occured, clear the requests
philpem@0 304 if (exception_q_w == `TRUE)
philpem@0 305 begin
philpem@0 306 jtag_break <= `FALSE;
philpem@0 307 jtag_reset <= `FALSE;
philpem@0 308 end
philpem@0 309 `endif
philpem@0 310 case (state)
philpem@0 311 `LM32_JTAG_STATE_READ_COMMAND:
philpem@0 312 begin
philpem@0 313 // Wait for rx register to toggle which indicates new data is available
philpem@18 314 if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
philpem@0 315 begin
philpem@0 316 command <= rx_byte[7:4];
philpem@0 317 case (rx_addr)
philpem@0 318 `ifdef CFG_DEBUG_ENABLED
philpem@0 319 `LM32_DP:
philpem@0 320 begin
philpem@0 321 case (rx_byte[7:4])
philpem@0 322 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 323 `LM32_DP_READ_MEMORY:
philpem@0 324 state <= `LM32_JTAG_STATE_READ_BYTE_0;
philpem@0 325 `LM32_DP_READ_SEQUENTIAL:
philpem@0 326 begin
philpem@0 327 {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
philpem@0 328 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
philpem@0 329 end
philpem@0 330 `LM32_DP_WRITE_MEMORY:
philpem@0 331 state <= `LM32_JTAG_STATE_READ_BYTE_0;
philpem@0 332 `LM32_DP_WRITE_SEQUENTIAL:
philpem@0 333 begin
philpem@0 334 {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
philpem@0 335 state <= 5;
philpem@0 336 end
philpem@0 337 `LM32_DP_WRITE_CSR:
philpem@0 338 state <= `LM32_JTAG_STATE_READ_BYTE_0;
philpem@0 339 `endif
philpem@0 340 `LM32_DP_BREAK:
philpem@0 341 begin
philpem@0 342 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 343 uart_rx_valid <= `FALSE;
philpem@0 344 uart_tx_valid <= `FALSE;
philpem@0 345 `endif
philpem@0 346 jtag_break <= `TRUE;
philpem@0 347 end
philpem@0 348 `LM32_DP_RESET:
philpem@0 349 begin
philpem@0 350 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 351 uart_rx_valid <= `FALSE;
philpem@0 352 uart_tx_valid <= `FALSE;
philpem@0 353 `endif
philpem@0 354 jtag_reset <= `TRUE;
philpem@0 355 end
philpem@0 356 endcase
philpem@0 357 end
philpem@0 358 `endif
philpem@0 359 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 360 `LM32_TX:
philpem@0 361 begin
philpem@0 362 uart_rx_byte <= rx_byte;
philpem@0 363 uart_rx_valid <= `TRUE;
philpem@0 364 end
philpem@0 365 `LM32_RX:
philpem@0 366 begin
philpem@0 367 jtag_reg_d <= uart_tx_byte;
philpem@0 368 uart_tx_valid <= `FALSE;
philpem@0 369 end
philpem@0 370 `endif
philpem@0 371 default:
philpem@0 372 ;
philpem@0 373 endcase
philpem@0 374 end
philpem@0 375 end
philpem@0 376 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 377 `LM32_JTAG_STATE_READ_BYTE_0:
philpem@0 378 begin
philpem@18 379 if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
philpem@0 380 begin
philpem@0 381 jtag_byte_0 <= rx_byte;
philpem@0 382 state <= `LM32_JTAG_STATE_READ_BYTE_1;
philpem@0 383 end
philpem@0 384 end
philpem@0 385 `LM32_JTAG_STATE_READ_BYTE_1:
philpem@0 386 begin
philpem@18 387 if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
philpem@0 388 begin
philpem@0 389 jtag_byte_1 <= rx_byte;
philpem@0 390 state <= `LM32_JTAG_STATE_READ_BYTE_2;
philpem@0 391 end
philpem@0 392 end
philpem@0 393 `LM32_JTAG_STATE_READ_BYTE_2:
philpem@0 394 begin
philpem@18 395 if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
philpem@0 396 begin
philpem@0 397 jtag_byte_2 <= rx_byte;
philpem@0 398 state <= `LM32_JTAG_STATE_READ_BYTE_3;
philpem@0 399 end
philpem@0 400 end
philpem@0 401 `LM32_JTAG_STATE_READ_BYTE_3:
philpem@0 402 begin
philpem@18 403 if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
philpem@0 404 begin
philpem@0 405 jtag_byte_3 <= rx_byte;
philpem@0 406 if (command == `LM32_DP_READ_MEMORY)
philpem@0 407 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
philpem@0 408 else
philpem@0 409 state <= `LM32_JTAG_STATE_READ_BYTE_4;
philpem@0 410 end
philpem@0 411 end
philpem@0 412 `LM32_JTAG_STATE_READ_BYTE_4:
philpem@0 413 begin
philpem@18 414 if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
philpem@0 415 begin
philpem@0 416 jtag_byte_4 <= rx_byte;
philpem@0 417 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
philpem@0 418 end
philpem@0 419 end
philpem@0 420 `LM32_JTAG_STATE_PROCESS_COMMAND:
philpem@0 421 begin
philpem@0 422 case (command)
philpem@0 423 `LM32_DP_READ_MEMORY,
philpem@0 424 `LM32_DP_READ_SEQUENTIAL:
philpem@0 425 begin
philpem@0 426 jtag_read_enable <= `TRUE;
philpem@0 427 processing <= `TRUE;
philpem@0 428 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
philpem@0 429 end
philpem@0 430 `LM32_DP_WRITE_MEMORY,
philpem@0 431 `LM32_DP_WRITE_SEQUENTIAL:
philpem@0 432 begin
philpem@0 433 jtag_write_enable <= `TRUE;
philpem@0 434 processing <= `TRUE;
philpem@0 435 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
philpem@0 436 end
philpem@0 437 `LM32_DP_WRITE_CSR:
philpem@0 438 begin
philpem@0 439 jtag_csr_write_enable <= `TRUE;
philpem@0 440 processing <= `TRUE;
philpem@0 441 state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
philpem@0 442 end
philpem@0 443 endcase
philpem@0 444 end
philpem@0 445 `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
philpem@0 446 begin
philpem@0 447 if (jtag_access_complete == `TRUE)
philpem@0 448 begin
philpem@0 449 jtag_read_enable <= `FALSE;
philpem@0 450 jtag_reg_d <= jtag_read_data;
philpem@0 451 jtag_write_enable <= `FALSE;
philpem@0 452 processing <= `FALSE;
philpem@0 453 state <= `LM32_JTAG_STATE_READ_COMMAND;
philpem@0 454 end
philpem@0 455 end
philpem@0 456 `LM32_JTAG_STATE_WAIT_FOR_CSR:
philpem@0 457 begin
philpem@0 458 jtag_csr_write_enable <= `FALSE;
philpem@0 459 processing <= `FALSE;
philpem@0 460 state <= `LM32_JTAG_STATE_READ_COMMAND;
philpem@0 461 end
philpem@0 462 `endif
philpem@0 463 endcase
philpem@0 464 end
philpem@0 465 end
philpem@0 466
philpem@0 467 endmodule
philpem@0 468
philpem@0 469 `endif