Sun, 04 Apr 2010 20:40:03 +0100
add lm32 source
philpem@0 | 1 | // ============================================================================= |
philpem@0 | 2 | // COPYRIGHT NOTICE |
philpem@0 | 3 | // Copyright 2006 (c) Lattice Semiconductor Corporation |
philpem@0 | 4 | // ALL RIGHTS RESERVED |
philpem@0 | 5 | // This confidential and proprietary software may be used only as authorised by |
philpem@0 | 6 | // a licensing agreement from Lattice Semiconductor Corporation. |
philpem@0 | 7 | // The entire notice above must be reproduced on all authorized copies and |
philpem@0 | 8 | // copies may only be made to the extent permitted by a licensing agreement from |
philpem@0 | 9 | // Lattice Semiconductor Corporation. |
philpem@0 | 10 | // |
philpem@0 | 11 | // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) |
philpem@0 | 12 | // 5555 NE Moore Court 408-826-6000 (other locations) |
philpem@0 | 13 | // Hillsboro, OR 97124 web : http://www.latticesemi.com/ |
philpem@0 | 14 | // U.S.A email: techsupport@latticesemi.com |
philpem@0 | 15 | // =============================================================================/ |
philpem@0 | 16 | // FILE DETAILS |
philpem@0 | 17 | // Project : LatticeMico32 |
philpem@0 | 18 | // File : er1.v |
philpem@0 | 19 | // Description: |
philpem@0 | 20 | // This module is where the ER1 register implemented. ER1 and ER2 registers |
philpem@0 | 21 | // can be registers implemented in Lattice FPGAs using normal FPGA's |
philpem@0 | 22 | // programmable logic resources. Once they are implemented, they can be |
philpem@0 | 23 | // accessed as if they are JTAG data registers through the FPGA JTAG port. |
philpem@0 | 24 | // In order to accessing these registers, JTAG instructions ER1(0x32) or |
philpem@0 | 25 | // ER2(0x38) needs to be written to the JTAG IR register for enabling the |
philpem@0 | 26 | // ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be |
philpem@0 | 27 | // enabled one at a time. Once they are enabled, they will be disabled if |
philpem@0 | 28 | // another JTAG instruction is written into the JTAG instruction register. |
philpem@0 | 29 | // The registers allow dynamically accessing the FPGA internal information |
philpem@0 | 30 | // even when the device is running. Therefore, they are very useful for some |
philpem@0 | 31 | // of the IP cores. In order to let ER1/ER2 registers shared by multiple IP |
philpem@0 | 32 | // cores or other designs, there is a ER1/ER2 structure patterned by Lattice. |
philpem@0 | 33 | // The ER1/ER2 structure allows only one ER1 register but more than one ER2 |
philpem@0 | 34 | // registers in an FPGA device. Please refer to the related document for |
philpem@0 | 35 | // this patterned ER1/ER2 structure. |
philpem@0 | 36 | // Dependencies : None |
philpem@0 | 37 | // Version : 6.0.14 |
philpem@0 | 38 | // : Initial Version |
philpem@0 | 39 | // Version : 7.0SP2, 3.0 |
philpem@0 | 40 | // : No Change |
philpem@0 | 41 | // Version : 3.1 |
philpem@0 | 42 | // : No Change |
philpem@0 | 43 | // ============================================================================= |
philpem@0 | 44 | module ER1 (input JTCK, |
philpem@0 | 45 | input JTDI, |
philpem@0 | 46 | output JTDO1, |
philpem@0 | 47 | output reg JTDO2, |
philpem@0 | 48 | input JSHIFT, |
philpem@0 | 49 | input JUPDATE, |
philpem@0 | 50 | input JRSTN, |
philpem@0 | 51 | input JCE1, |
philpem@0 | 52 | input [14:0] ER2_TDO, |
philpem@0 | 53 | output reg [14:0] IP_ENABLE, |
philpem@0 | 54 | input ISPTRACY_ER2_TDO, |
philpem@0 | 55 | output ISPTRACY_ENABLE, |
philpem@0 | 56 | output CONTROL_DATAN)/* synthesis syn_hier = hard */; |
philpem@0 | 57 | |
philpem@0 | 58 | |
philpem@0 | 59 | wire controlDataNBit; |
philpem@0 | 60 | wire ispTracyEnableBit; |
philpem@0 | 61 | wire [3:0] encodedIpEnableBits; |
philpem@0 | 62 | wire [9:0] er1TdiBit; |
philpem@0 | 63 | wire captureDrER1; |
philpem@0 | 64 | |
philpem@0 | 65 | |
philpem@0 | 66 | assign JTDO1 = er1TdiBit[0]; |
philpem@0 | 67 | |
philpem@0 | 68 | TYPEB BIT0 (.CLK(JTCK), |
philpem@0 | 69 | .RESET_N(JRSTN), |
philpem@0 | 70 | .CLKEN(JCE1), |
philpem@0 | 71 | .TDI(er1TdiBit[1]), |
philpem@0 | 72 | .TDO(er1TdiBit[0]), |
philpem@0 | 73 | .DATA_IN(1'b0), |
philpem@0 | 74 | .CAPTURE_DR(captureDrER1)); |
philpem@0 | 75 | |
philpem@0 | 76 | TYPEB BIT1 (.CLK(JTCK), |
philpem@0 | 77 | .RESET_N(JRSTN), |
philpem@0 | 78 | .CLKEN(JCE1), |
philpem@0 | 79 | .TDI(er1TdiBit[2]), |
philpem@0 | 80 | .TDO(er1TdiBit[1]), |
philpem@0 | 81 | .DATA_IN(1'b0), |
philpem@0 | 82 | .CAPTURE_DR(captureDrER1)); |
philpem@0 | 83 | |
philpem@0 | 84 | TYPEB BIT2 (.CLK(JTCK), |
philpem@0 | 85 | .RESET_N(JRSTN), |
philpem@0 | 86 | .CLKEN(JCE1), |
philpem@0 | 87 | .TDI(er1TdiBit[3]), |
philpem@0 | 88 | .TDO(er1TdiBit[2]), |
philpem@0 | 89 | .DATA_IN(1'b1), |
philpem@0 | 90 | .CAPTURE_DR(captureDrER1)); |
philpem@0 | 91 | |
philpem@0 | 92 | TYPEA BIT3 (.CLK(JTCK), |
philpem@0 | 93 | .RESET_N(JRSTN), |
philpem@0 | 94 | .CLKEN(JCE1), |
philpem@0 | 95 | .TDI(er1TdiBit[4]), |
philpem@0 | 96 | .TDO(er1TdiBit[3]), |
philpem@0 | 97 | .DATA_OUT(controlDataNBit), |
philpem@0 | 98 | .DATA_IN(controlDataNBit), |
philpem@0 | 99 | .CAPTURE_DR(captureDrER1), |
philpem@0 | 100 | .UPDATE_DR(JUPDATE)); |
philpem@0 | 101 | |
philpem@0 | 102 | assign CONTROL_DATAN = controlDataNBit; |
philpem@0 | 103 | |
philpem@0 | 104 | TYPEA BIT4 (.CLK(JTCK), |
philpem@0 | 105 | .RESET_N(JRSTN), |
philpem@0 | 106 | .CLKEN(JCE1), |
philpem@0 | 107 | .TDI(er1TdiBit[5]), |
philpem@0 | 108 | .TDO(er1TdiBit[4]), |
philpem@0 | 109 | .DATA_OUT(ispTracyEnableBit), |
philpem@0 | 110 | .DATA_IN(ispTracyEnableBit), |
philpem@0 | 111 | .CAPTURE_DR(captureDrER1), |
philpem@0 | 112 | .UPDATE_DR(JUPDATE) |
philpem@0 | 113 | ); |
philpem@0 | 114 | |
philpem@0 | 115 | assign ISPTRACY_ENABLE = ispTracyEnableBit; |
philpem@0 | 116 | |
philpem@0 | 117 | TYPEA BIT5 (.CLK(JTCK), |
philpem@0 | 118 | .RESET_N(JRSTN), |
philpem@0 | 119 | .CLKEN(JCE1), |
philpem@0 | 120 | .TDI(er1TdiBit[6]), |
philpem@0 | 121 | .TDO(er1TdiBit[5]), |
philpem@0 | 122 | .DATA_OUT(encodedIpEnableBits[0]), |
philpem@0 | 123 | .DATA_IN(encodedIpEnableBits[0]), |
philpem@0 | 124 | .CAPTURE_DR(captureDrER1), |
philpem@0 | 125 | .UPDATE_DR(JUPDATE)); |
philpem@0 | 126 | |
philpem@0 | 127 | TYPEA BIT6 (.CLK(JTCK), |
philpem@0 | 128 | .RESET_N(JRSTN), |
philpem@0 | 129 | .CLKEN(JCE1), |
philpem@0 | 130 | .TDI(er1TdiBit[7]), |
philpem@0 | 131 | .TDO(er1TdiBit[6]), |
philpem@0 | 132 | .DATA_OUT(encodedIpEnableBits[1]), |
philpem@0 | 133 | .DATA_IN(encodedIpEnableBits[1]), |
philpem@0 | 134 | .CAPTURE_DR(captureDrER1), |
philpem@0 | 135 | .UPDATE_DR(JUPDATE)); |
philpem@0 | 136 | |
philpem@0 | 137 | TYPEA BIT7 (.CLK(JTCK), |
philpem@0 | 138 | .RESET_N(JRSTN), |
philpem@0 | 139 | .CLKEN(JCE1), |
philpem@0 | 140 | .TDI(er1TdiBit[8]), |
philpem@0 | 141 | .TDO(er1TdiBit[7]), |
philpem@0 | 142 | .DATA_OUT(encodedIpEnableBits[2]), |
philpem@0 | 143 | .DATA_IN(encodedIpEnableBits[2]), |
philpem@0 | 144 | .CAPTURE_DR(captureDrER1), |
philpem@0 | 145 | .UPDATE_DR(JUPDATE)); |
philpem@0 | 146 | |
philpem@0 | 147 | TYPEA BIT8 (.CLK(JTCK), |
philpem@0 | 148 | .RESET_N(JRSTN), |
philpem@0 | 149 | .CLKEN(JCE1), |
philpem@0 | 150 | .TDI(er1TdiBit[9]), |
philpem@0 | 151 | .TDO(er1TdiBit[8]), |
philpem@0 | 152 | .DATA_OUT(encodedIpEnableBits[3]), |
philpem@0 | 153 | .DATA_IN(encodedIpEnableBits[3]), |
philpem@0 | 154 | .CAPTURE_DR(captureDrER1), |
philpem@0 | 155 | .UPDATE_DR(JUPDATE) |
philpem@0 | 156 | ); |
philpem@0 | 157 | |
philpem@0 | 158 | assign er1TdiBit[9] = JTDI; |
philpem@0 | 159 | assign captureDrER1 = !JSHIFT & JCE1; |
philpem@0 | 160 | |
philpem@0 | 161 | always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO) |
philpem@0 | 162 | begin |
philpem@0 | 163 | case (encodedIpEnableBits) |
philpem@0 | 164 | 4'h0: begin |
philpem@0 | 165 | IP_ENABLE <= 15'b000000000000000; |
philpem@0 | 166 | JTDO2 <= ISPTRACY_ER2_TDO; |
philpem@0 | 167 | end |
philpem@0 | 168 | 4'h1: begin |
philpem@0 | 169 | IP_ENABLE <= 15'b000000000000001; |
philpem@0 | 170 | JTDO2 <= ER2_TDO[0]; |
philpem@0 | 171 | end |
philpem@0 | 172 | 4'h2: begin |
philpem@0 | 173 | IP_ENABLE <= 15'b000000000000010; |
philpem@0 | 174 | JTDO2 <= ER2_TDO[1]; |
philpem@0 | 175 | end |
philpem@0 | 176 | 4'h3: begin |
philpem@0 | 177 | IP_ENABLE <= 15'b000000000000100; |
philpem@0 | 178 | JTDO2 <= ER2_TDO[2]; |
philpem@0 | 179 | end |
philpem@0 | 180 | 4'h4: begin |
philpem@0 | 181 | IP_ENABLE <= 15'b000000000001000; |
philpem@0 | 182 | JTDO2 <= ER2_TDO[3]; |
philpem@0 | 183 | end |
philpem@0 | 184 | 4'h5: begin |
philpem@0 | 185 | IP_ENABLE <= 15'b000000000010000; |
philpem@0 | 186 | JTDO2 <= ER2_TDO[4]; |
philpem@0 | 187 | end |
philpem@0 | 188 | 4'h6: begin |
philpem@0 | 189 | IP_ENABLE <= 15'b000000000100000; |
philpem@0 | 190 | JTDO2 <= ER2_TDO[5]; |
philpem@0 | 191 | end |
philpem@0 | 192 | 4'h7: begin |
philpem@0 | 193 | IP_ENABLE <= 15'b000000001000000; |
philpem@0 | 194 | JTDO2 <= ER2_TDO[6]; |
philpem@0 | 195 | end |
philpem@0 | 196 | 4'h8: begin |
philpem@0 | 197 | IP_ENABLE <= 15'b000000010000000; |
philpem@0 | 198 | JTDO2 <= ER2_TDO[7]; |
philpem@0 | 199 | end |
philpem@0 | 200 | 4'h9: begin |
philpem@0 | 201 | IP_ENABLE <= 15'b000000100000000; |
philpem@0 | 202 | JTDO2 <= ER2_TDO[8]; |
philpem@0 | 203 | end |
philpem@0 | 204 | 4'hA: begin |
philpem@0 | 205 | IP_ENABLE <= 15'b000001000000000; |
philpem@0 | 206 | JTDO2 <= ER2_TDO[9]; |
philpem@0 | 207 | end |
philpem@0 | 208 | 4'hB: begin |
philpem@0 | 209 | IP_ENABLE <= 15'b000010000000000; |
philpem@0 | 210 | JTDO2 <= ER2_TDO[10]; |
philpem@0 | 211 | end |
philpem@0 | 212 | 4'hC: begin |
philpem@0 | 213 | IP_ENABLE <= 15'b000100000000000; |
philpem@0 | 214 | JTDO2 <= ER2_TDO[11]; |
philpem@0 | 215 | end |
philpem@0 | 216 | 4'hD: begin |
philpem@0 | 217 | IP_ENABLE <= 15'b001000000000000; |
philpem@0 | 218 | JTDO2 <= ER2_TDO[12]; |
philpem@0 | 219 | end |
philpem@0 | 220 | 4'hE: begin |
philpem@0 | 221 | IP_ENABLE <= 15'b010000000000000; |
philpem@0 | 222 | JTDO2 <= ER2_TDO[13]; |
philpem@0 | 223 | end |
philpem@0 | 224 | 4'hF: begin |
philpem@0 | 225 | IP_ENABLE <= 15'b100000000000000; |
philpem@0 | 226 | JTDO2 <= ER2_TDO[14]; |
philpem@0 | 227 | end |
philpem@0 | 228 | endcase |
philpem@0 | 229 | end |
philpem@0 | 230 | endmodule |