Sun, 04 Apr 2010 20:40:03 +0100
add lm32 source
philpem@0 | 1 | // ============================================================================= |
philpem@0 | 2 | // COPYRIGHT NOTICE |
philpem@0 | 3 | // Copyright 2006 (c) Lattice Semiconductor Corporation |
philpem@0 | 4 | // ALL RIGHTS RESERVED |
philpem@0 | 5 | // This confidential and proprietary software may be used only as authorised by |
philpem@0 | 6 | // a licensing agreement from Lattice Semiconductor Corporation. |
philpem@0 | 7 | // The entire notice above must be reproduced on all authorized copies and |
philpem@0 | 8 | // copies may only be made to the extent permitted by a licensing agreement from |
philpem@0 | 9 | // Lattice Semiconductor Corporation. |
philpem@0 | 10 | // |
philpem@0 | 11 | // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) |
philpem@0 | 12 | // 5555 NE Moore Court 408-826-6000 (other locations) |
philpem@0 | 13 | // Hillsboro, OR 97124 web : http://www.latticesemi.com/ |
philpem@0 | 14 | // U.S.A email: techsupport@latticesemi.com |
philpem@0 | 15 | // =============================================================================/ |
philpem@0 | 16 | // FILE DETAILS |
philpem@0 | 17 | // Project : LatticeMico32 |
philpem@0 | 18 | // File : lm32_top.v |
philpem@0 | 19 | // Title : Top-level of CPU. |
philpem@0 | 20 | // Dependencies : lm32_include.v |
philpem@0 | 21 | // Version : 6.1.17 |
philpem@0 | 22 | // : removed SPI - 04/12/07 |
philpem@0 | 23 | // Version : 7.0SP2, 3.0 |
philpem@0 | 24 | // : No Change |
philpem@0 | 25 | // Version : 3.1 |
philpem@0 | 26 | // : No Change |
philpem@0 | 27 | // ============================================================================= |
philpem@0 | 28 | |
philpem@0 | 29 | `include "lm32_include.v" |
philpem@0 | 30 | |
philpem@0 | 31 | ///////////////////////////////////////////////////// |
philpem@0 | 32 | // Module interface |
philpem@0 | 33 | ///////////////////////////////////////////////////// |
philpem@0 | 34 | |
philpem@0 | 35 | module lm32_top ( |
philpem@0 | 36 | // ----- Inputs ------- |
philpem@0 | 37 | clk_i, |
philpem@0 | 38 | rst_i, |
philpem@0 | 39 | // From external devices |
philpem@0 | 40 | `ifdef CFG_INTERRUPTS_ENABLED |
philpem@0 | 41 | interrupt_n, |
philpem@0 | 42 | `endif |
philpem@0 | 43 | // From user logic |
philpem@0 | 44 | `ifdef CFG_USER_ENABLED |
philpem@0 | 45 | user_result, |
philpem@0 | 46 | user_complete, |
philpem@0 | 47 | `endif |
philpem@0 | 48 | `ifdef CFG_IWB_ENABLED |
philpem@0 | 49 | // Instruction Wishbone master |
philpem@0 | 50 | I_DAT_I, |
philpem@0 | 51 | I_ACK_I, |
philpem@0 | 52 | I_ERR_I, |
philpem@0 | 53 | I_RTY_I, |
philpem@0 | 54 | `endif |
philpem@0 | 55 | // Data Wishbone master |
philpem@0 | 56 | D_DAT_I, |
philpem@0 | 57 | D_ACK_I, |
philpem@0 | 58 | D_ERR_I, |
philpem@0 | 59 | D_RTY_I, |
philpem@0 | 60 | // Debug Slave port WishboneInterface |
philpem@0 | 61 | DEBUG_ADR_I, |
philpem@0 | 62 | DEBUG_DAT_I, |
philpem@0 | 63 | DEBUG_SEL_I, |
philpem@0 | 64 | DEBUG_WE_I, |
philpem@0 | 65 | DEBUG_CTI_I, |
philpem@0 | 66 | DEBUG_BTE_I, |
philpem@0 | 67 | DEBUG_LOCK_I, |
philpem@0 | 68 | DEBUG_CYC_I, |
philpem@0 | 69 | DEBUG_STB_I, |
philpem@0 | 70 | // ----- Outputs ------- |
philpem@0 | 71 | `ifdef CFG_USER_ENABLED |
philpem@0 | 72 | user_valid, |
philpem@0 | 73 | user_opcode, |
philpem@0 | 74 | user_operand_0, |
philpem@0 | 75 | user_operand_1, |
philpem@0 | 76 | `endif |
philpem@0 | 77 | `ifdef CFG_IWB_ENABLED |
philpem@0 | 78 | // Instruction Wishbone master |
philpem@0 | 79 | I_DAT_O, |
philpem@0 | 80 | I_ADR_O, |
philpem@0 | 81 | I_CYC_O, |
philpem@0 | 82 | I_SEL_O, |
philpem@0 | 83 | I_STB_O, |
philpem@0 | 84 | I_WE_O, |
philpem@0 | 85 | I_CTI_O, |
philpem@0 | 86 | I_LOCK_O, |
philpem@0 | 87 | I_BTE_O, |
philpem@0 | 88 | `endif |
philpem@0 | 89 | // Data Wishbone master |
philpem@0 | 90 | D_DAT_O, |
philpem@0 | 91 | D_ADR_O, |
philpem@0 | 92 | D_CYC_O, |
philpem@0 | 93 | D_SEL_O, |
philpem@0 | 94 | D_STB_O, |
philpem@0 | 95 | D_WE_O, |
philpem@0 | 96 | D_CTI_O, |
philpem@0 | 97 | D_LOCK_O, |
philpem@0 | 98 | D_BTE_O, |
philpem@0 | 99 | // Debug Slave port WishboneInterface |
philpem@0 | 100 | DEBUG_ACK_O, |
philpem@0 | 101 | DEBUG_ERR_O, |
philpem@0 | 102 | DEBUG_RTY_O, |
philpem@0 | 103 | DEBUG_DAT_O |
philpem@0 | 104 | ); |
philpem@0 | 105 | |
philpem@0 | 106 | ///////////////////////////////////////////////////// |
philpem@0 | 107 | // Inputs |
philpem@0 | 108 | ///////////////////////////////////////////////////// |
philpem@0 | 109 | |
philpem@0 | 110 | input clk_i; // Clock |
philpem@0 | 111 | input rst_i; // Reset |
philpem@0 | 112 | |
philpem@0 | 113 | `ifdef CFG_INTERRUPTS_ENABLED |
philpem@0 | 114 | input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low |
philpem@0 | 115 | `endif |
philpem@0 | 116 | |
philpem@0 | 117 | `ifdef CFG_USER_ENABLED |
philpem@0 | 118 | input [`LM32_WORD_RNG] user_result; // User-defined instruction result |
philpem@0 | 119 | input user_complete; // Indicates the user-defined instruction result is valid |
philpem@0 | 120 | `endif |
philpem@0 | 121 | |
philpem@0 | 122 | `ifdef CFG_IWB_ENABLED |
philpem@0 | 123 | input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data |
philpem@0 | 124 | input I_ACK_I; // Instruction Wishbone interface acknowledgement |
philpem@0 | 125 | input I_ERR_I; // Instruction Wishbone interface error |
philpem@0 | 126 | input I_RTY_I; // Instruction Wishbone interface retry |
philpem@0 | 127 | `endif |
philpem@0 | 128 | |
philpem@0 | 129 | input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data |
philpem@0 | 130 | input D_ACK_I; // Data Wishbone interface acknowledgement |
philpem@0 | 131 | input D_ERR_I; // Data Wishbone interface error |
philpem@0 | 132 | input D_RTY_I; // Data Wishbone interface retry |
philpem@0 | 133 | |
philpem@0 | 134 | input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address |
philpem@0 | 135 | input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data |
philpem@0 | 136 | input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select |
philpem@0 | 137 | input DEBUG_WE_I; // Debug monitor Wishbone interface write enable |
philpem@0 | 138 | input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type |
philpem@0 | 139 | input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type |
philpem@0 | 140 | input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer |
philpem@0 | 141 | input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle |
philpem@0 | 142 | input DEBUG_STB_I; // Debug monitor Wishbone interface strobe |
philpem@0 | 143 | |
philpem@0 | 144 | ///////////////////////////////////////////////////// |
philpem@0 | 145 | // Outputs |
philpem@0 | 146 | ///////////////////////////////////////////////////// |
philpem@0 | 147 | |
philpem@0 | 148 | `ifdef CFG_USER_ENABLED |
philpem@0 | 149 | output user_valid; // Indicates that user_opcode and user_operand_* are valid |
philpem@0 | 150 | wire user_valid; |
philpem@0 | 151 | output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode |
philpem@0 | 152 | reg [`LM32_USER_OPCODE_RNG] user_opcode; |
philpem@0 | 153 | output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction |
philpem@0 | 154 | wire [`LM32_WORD_RNG] user_operand_0; |
philpem@0 | 155 | output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction |
philpem@0 | 156 | wire [`LM32_WORD_RNG] user_operand_1; |
philpem@0 | 157 | `endif |
philpem@0 | 158 | |
philpem@0 | 159 | `ifdef CFG_IWB_ENABLED |
philpem@0 | 160 | output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data |
philpem@0 | 161 | wire [`LM32_WORD_RNG] I_DAT_O; |
philpem@0 | 162 | output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address |
philpem@0 | 163 | wire [`LM32_WORD_RNG] I_ADR_O; |
philpem@0 | 164 | output I_CYC_O; // Instruction Wishbone interface cycle |
philpem@0 | 165 | wire I_CYC_O; |
philpem@0 | 166 | output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select |
philpem@0 | 167 | wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; |
philpem@0 | 168 | output I_STB_O; // Instruction Wishbone interface strobe |
philpem@0 | 169 | wire I_STB_O; |
philpem@0 | 170 | output I_WE_O; // Instruction Wishbone interface write enable |
philpem@0 | 171 | wire I_WE_O; |
philpem@0 | 172 | output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type |
philpem@0 | 173 | wire [`LM32_CTYPE_RNG] I_CTI_O; |
philpem@0 | 174 | output I_LOCK_O; // Instruction Wishbone interface lock bus |
philpem@0 | 175 | wire I_LOCK_O; |
philpem@0 | 176 | output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type |
philpem@0 | 177 | wire [`LM32_BTYPE_RNG] I_BTE_O; |
philpem@0 | 178 | `endif |
philpem@0 | 179 | |
philpem@0 | 180 | output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data |
philpem@0 | 181 | wire [`LM32_WORD_RNG] D_DAT_O; |
philpem@0 | 182 | output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address |
philpem@0 | 183 | wire [`LM32_WORD_RNG] D_ADR_O; |
philpem@0 | 184 | output D_CYC_O; // Data Wishbone interface cycle |
philpem@0 | 185 | wire D_CYC_O; |
philpem@0 | 186 | output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select |
philpem@0 | 187 | wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; |
philpem@0 | 188 | output D_STB_O; // Data Wishbone interface strobe |
philpem@0 | 189 | wire D_STB_O; |
philpem@0 | 190 | output D_WE_O; // Data Wishbone interface write enable |
philpem@0 | 191 | wire D_WE_O; |
philpem@0 | 192 | output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type |
philpem@0 | 193 | wire [`LM32_CTYPE_RNG] D_CTI_O; |
philpem@0 | 194 | output D_LOCK_O; // Date Wishbone interface lock bus |
philpem@0 | 195 | wire D_LOCK_O; |
philpem@0 | 196 | output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type |
philpem@0 | 197 | wire [`LM32_BTYPE_RNG] D_BTE_O; |
philpem@0 | 198 | |
philpem@0 | 199 | output DEBUG_ACK_O; // Debug monitor Wishbone ack |
philpem@0 | 200 | wire DEBUG_ACK_O; |
philpem@0 | 201 | output DEBUG_ERR_O; // Debug monitor Wishbone error |
philpem@0 | 202 | wire DEBUG_ERR_O; |
philpem@0 | 203 | output DEBUG_RTY_O; // Debug monitor Wishbone retry |
philpem@0 | 204 | wire DEBUG_RTY_O; |
philpem@0 | 205 | output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data |
philpem@0 | 206 | wire [`LM32_WORD_RNG] DEBUG_DAT_O; |
philpem@0 | 207 | |
philpem@0 | 208 | ///////////////////////////////////////////////////// |
philpem@0 | 209 | // Internal nets and registers |
philpem@0 | 210 | ///////////////////////////////////////////////////// |
philpem@0 | 211 | |
philpem@0 | 212 | `ifdef CFG_JTAG_ENABLED |
philpem@0 | 213 | // Signals between JTAG interface and CPU |
philpem@0 | 214 | wire [`LM32_BYTE_RNG] jtag_reg_d; |
philpem@0 | 215 | wire [`LM32_BYTE_RNG] jtag_reg_q; |
philpem@0 | 216 | wire jtag_update; |
philpem@0 | 217 | wire [2:0] jtag_reg_addr_d; |
philpem@0 | 218 | wire [2:0] jtag_reg_addr_q; |
philpem@0 | 219 | wire jtck; |
philpem@0 | 220 | wire jrstn; |
philpem@0 | 221 | `endif |
philpem@0 | 222 | |
philpem@0 | 223 | `ifdef CFG_TRACE_ENABLED |
philpem@0 | 224 | // PC trace signals |
philpem@0 | 225 | wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction) |
philpem@0 | 226 | wire trace_pc_valid; // Indicates that a new trace PC is valid |
philpem@0 | 227 | wire trace_exception; // Indicates an exception has occured |
philpem@0 | 228 | wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured |
philpem@0 | 229 | wire trace_eret; // Indicates an eret instruction has been executed |
philpem@0 | 230 | `ifdef CFG_DEBUG_ENABLED |
philpem@0 | 231 | wire trace_bret; // Indicates a bret instruction has been executed |
philpem@0 | 232 | `endif |
philpem@0 | 233 | `endif |
philpem@0 | 234 | |
philpem@0 | 235 | ///////////////////////////////////////////////////// |
philpem@0 | 236 | // Functions |
philpem@0 | 237 | ///////////////////////////////////////////////////// |
philpem@0 | 238 | |
philpem@0 | 239 | `include "lm32_functions.v" |
philpem@0 | 240 | ///////////////////////////////////////////////////// |
philpem@0 | 241 | // Instantiations |
philpem@0 | 242 | ///////////////////////////////////////////////////// |
philpem@0 | 243 | |
philpem@0 | 244 | // LM32 CPU |
philpem@0 | 245 | lm32_cpu cpu ( |
philpem@0 | 246 | // ----- Inputs ------- |
philpem@0 | 247 | .clk_i (clk_i), |
philpem@0 | 248 | `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE |
philpem@0 | 249 | .clk_n_i (clk_n), |
philpem@0 | 250 | `endif |
philpem@0 | 251 | .rst_i (rst_i), |
philpem@0 | 252 | // From external devices |
philpem@0 | 253 | `ifdef CFG_INTERRUPTS_ENABLED |
philpem@0 | 254 | .interrupt_n (interrupt_n), |
philpem@0 | 255 | `endif |
philpem@0 | 256 | // From user logic |
philpem@0 | 257 | `ifdef CFG_USER_ENABLED |
philpem@0 | 258 | .user_result (user_result), |
philpem@0 | 259 | .user_complete (user_complete), |
philpem@0 | 260 | `endif |
philpem@0 | 261 | `ifdef CFG_JTAG_ENABLED |
philpem@0 | 262 | // From JTAG |
philpem@0 | 263 | .jtag_clk (jtck), |
philpem@0 | 264 | .jtag_update (jtag_update), |
philpem@0 | 265 | .jtag_reg_q (jtag_reg_q), |
philpem@0 | 266 | .jtag_reg_addr_q (jtag_reg_addr_q), |
philpem@0 | 267 | `endif |
philpem@0 | 268 | `ifdef CFG_IWB_ENABLED |
philpem@0 | 269 | // Instruction Wishbone master |
philpem@0 | 270 | .I_DAT_I (I_DAT_I), |
philpem@0 | 271 | .I_ACK_I (I_ACK_I), |
philpem@0 | 272 | .I_ERR_I (I_ERR_I), |
philpem@0 | 273 | .I_RTY_I (I_RTY_I), |
philpem@0 | 274 | `endif |
philpem@0 | 275 | // Data Wishbone master |
philpem@0 | 276 | .D_DAT_I (D_DAT_I), |
philpem@0 | 277 | .D_ACK_I (D_ACK_I), |
philpem@0 | 278 | .D_ERR_I (D_ERR_I), |
philpem@0 | 279 | .D_RTY_I (D_RTY_I), |
philpem@0 | 280 | // ----- Outputs ------- |
philpem@0 | 281 | `ifdef CFG_TRACE_ENABLED |
philpem@0 | 282 | .trace_pc (trace_pc), |
philpem@0 | 283 | .trace_pc_valid (trace_pc_valid), |
philpem@0 | 284 | .trace_exception (trace_exception), |
philpem@0 | 285 | .trace_eid (trace_eid), |
philpem@0 | 286 | .trace_eret (trace_eret), |
philpem@0 | 287 | `ifdef CFG_DEBUG_ENABLED |
philpem@0 | 288 | .trace_bret (trace_bret), |
philpem@0 | 289 | `endif |
philpem@0 | 290 | `endif |
philpem@0 | 291 | `ifdef CFG_JTAG_ENABLED |
philpem@0 | 292 | .jtag_reg_d (jtag_reg_d), |
philpem@0 | 293 | .jtag_reg_addr_d (jtag_reg_addr_d), |
philpem@0 | 294 | `endif |
philpem@0 | 295 | `ifdef CFG_USER_ENABLED |
philpem@0 | 296 | .user_valid (user_valid), |
philpem@0 | 297 | .user_opcode (user_opcode), |
philpem@0 | 298 | .user_operand_0 (user_operand_0), |
philpem@0 | 299 | .user_operand_1 (user_operand_1), |
philpem@0 | 300 | `endif |
philpem@0 | 301 | `ifdef CFG_IWB_ENABLED |
philpem@0 | 302 | // Instruction Wishbone master |
philpem@0 | 303 | .I_DAT_O (I_DAT_O), |
philpem@0 | 304 | .I_ADR_O (I_ADR_O), |
philpem@0 | 305 | .I_CYC_O (I_CYC_O), |
philpem@0 | 306 | .I_SEL_O (I_SEL_O), |
philpem@0 | 307 | .I_STB_O (I_STB_O), |
philpem@0 | 308 | .I_WE_O (I_WE_O), |
philpem@0 | 309 | .I_CTI_O (I_CTI_O), |
philpem@0 | 310 | .I_LOCK_O (I_LOCK_O), |
philpem@0 | 311 | .I_BTE_O (I_BTE_O), |
philpem@0 | 312 | `endif |
philpem@0 | 313 | // Data Wishbone master |
philpem@0 | 314 | .D_DAT_O (D_DAT_O), |
philpem@0 | 315 | .D_ADR_O (D_ADR_O), |
philpem@0 | 316 | .D_CYC_O (D_CYC_O), |
philpem@0 | 317 | .D_SEL_O (D_SEL_O), |
philpem@0 | 318 | .D_STB_O (D_STB_O), |
philpem@0 | 319 | .D_WE_O (D_WE_O), |
philpem@0 | 320 | .D_CTI_O (D_CTI_O), |
philpem@0 | 321 | .D_LOCK_O (D_LOCK_O), |
philpem@0 | 322 | .D_BTE_O (D_BTE_O) |
philpem@0 | 323 | ); |
philpem@0 | 324 | |
philpem@0 | 325 | wire TRACE_ACK_O; |
philpem@0 | 326 | wire [`LM32_WORD_RNG] TRACE_DAT_O; |
philpem@0 | 327 | `ifdef CFG_TRACE_ENABLED |
philpem@0 | 328 | lm32_trace trace_module (.clk_i (clk_i), |
philpem@0 | 329 | .rst_i (rst_i), |
philpem@0 | 330 | .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]), |
philpem@0 | 331 | .we_i (DEBUG_WE_I), |
philpem@0 | 332 | .sel_i (DEBUG_SEL_I), |
philpem@0 | 333 | .dat_i (DEBUG_DAT_I), |
philpem@0 | 334 | .adr_i (DEBUG_ADR_I), |
philpem@0 | 335 | .trace_pc (trace_pc), |
philpem@0 | 336 | .trace_eid (trace_eid), |
philpem@0 | 337 | .trace_eret (trace_eret), |
philpem@0 | 338 | .trace_bret (trace_bret), |
philpem@0 | 339 | .trace_pc_valid (trace_pc_valid), |
philpem@0 | 340 | .trace_exception (trace_exception), |
philpem@0 | 341 | .ack_o (TRACE_ACK_O), |
philpem@0 | 342 | .dat_o (TRACE_DAT_O)); |
philpem@0 | 343 | `else |
philpem@0 | 344 | assign TRACE_ACK_O = 0; |
philpem@0 | 345 | assign TRACE_DAT_O = 0; |
philpem@0 | 346 | `endif |
philpem@0 | 347 | `ifdef DEBUG_ROM |
philpem@0 | 348 | wire ROM_ACK_O; |
philpem@0 | 349 | wire [`LM32_WORD_RNG] ROM_DAT_O; |
philpem@0 | 350 | |
philpem@0 | 351 | assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O; |
philpem@0 | 352 | assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O; |
philpem@0 | 353 | |
philpem@0 | 354 | // ROM monitor |
philpem@0 | 355 | lm32_monitor debug_rom ( |
philpem@0 | 356 | // ----- Inputs ------- |
philpem@0 | 357 | .clk_i (clk_i), |
philpem@0 | 358 | .rst_i (rst_i), |
philpem@0 | 359 | .MON_ADR_I (DEBUG_ADR_I), |
philpem@0 | 360 | .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]), |
philpem@0 | 361 | .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]), |
philpem@0 | 362 | .MON_WE_I (DEBUG_WE_I), |
philpem@0 | 363 | .MON_SEL_I (DEBUG_SEL_I), |
philpem@0 | 364 | .MON_DAT_I (DEBUG_DAT_I), |
philpem@0 | 365 | .MON_CTI_I (DEBUG_CTI_I), |
philpem@0 | 366 | .MON_BTE_I (DEBUG_BTE_I), |
philpem@0 | 367 | .MON_LOCK_I (DEBUG_LOCK_I), |
philpem@0 | 368 | // ----- Outputs ------ |
philpem@0 | 369 | .MON_RTY_O (DEBUG_RTY_O), |
philpem@0 | 370 | .MON_ERR_O (DEBUG_ERR_O), |
philpem@0 | 371 | .MON_ACK_O (ROM_ACK_O), |
philpem@0 | 372 | .MON_DAT_O (ROM_DAT_O) |
philpem@0 | 373 | ); |
philpem@0 | 374 | `endif |
philpem@0 | 375 | |
philpem@0 | 376 | `ifdef CFG_JTAG_ENABLED |
philpem@0 | 377 | // JTAG cores |
philpem@0 | 378 | jtag_cores jtag_cores ( |
philpem@0 | 379 | // ----- Inputs ----- |
philpem@0 | 380 | `ifdef INCLUDE_LM32 |
philpem@0 | 381 | .reg_d (jtag_reg_d), |
philpem@0 | 382 | .reg_addr_d (jtag_reg_addr_d), |
philpem@0 | 383 | `endif |
philpem@0 | 384 | // ----- Outputs ----- |
philpem@0 | 385 | `ifdef INCLUDE_LM32 |
philpem@0 | 386 | .reg_update (jtag_update), |
philpem@0 | 387 | .reg_q (jtag_reg_q), |
philpem@0 | 388 | .reg_addr_q (jtag_reg_addr_q), |
philpem@0 | 389 | `endif |
philpem@0 | 390 | .jtck (jtck), |
philpem@0 | 391 | .jrstn (jrstn) |
philpem@0 | 392 | ); |
philpem@0 | 393 | `endif |
philpem@0 | 394 | |
philpem@0 | 395 | endmodule |