er1.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
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philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : er1.v
philpem@0 40 // Description:
philpem@0 41 // This module is where the ER1 register implemented. ER1 and ER2 registers
philpem@0 42 // can be registers implemented in Lattice FPGAs using normal FPGA's
philpem@0 43 // programmable logic resources. Once they are implemented, they can be
philpem@0 44 // accessed as if they are JTAG data registers through the FPGA JTAG port.
philpem@0 45 // In order to accessing these registers, JTAG instructions ER1(0x32) or
philpem@0 46 // ER2(0x38) needs to be written to the JTAG IR register for enabling the
philpem@0 47 // ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be
philpem@0 48 // enabled one at a time. Once they are enabled, they will be disabled if
philpem@0 49 // another JTAG instruction is written into the JTAG instruction register.
philpem@0 50 // The registers allow dynamically accessing the FPGA internal information
philpem@0 51 // even when the device is running. Therefore, they are very useful for some
philpem@0 52 // of the IP cores. In order to let ER1/ER2 registers shared by multiple IP
philpem@0 53 // cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
philpem@0 54 // The ER1/ER2 structure allows only one ER1 register but more than one ER2
philpem@0 55 // registers in an FPGA device. Please refer to the related document for
philpem@0 56 // this patterned ER1/ER2 structure.
philpem@0 57 // Dependencies : None
philpem@0 58 // Version : 6.0.14
philpem@0 59 // : Initial Version
philpem@0 60 // Version : 7.0SP2, 3.0
philpem@0 61 // : No Change
philpem@0 62 // Version : 3.1
philpem@0 63 // : No Change
philpem@0 64 // =============================================================================
philpem@0 65 module ER1 (input JTCK,
philpem@0 66 input JTDI,
philpem@0 67 output JTDO1,
philpem@0 68 output reg JTDO2,
philpem@0 69 input JSHIFT,
philpem@0 70 input JUPDATE,
philpem@0 71 input JRSTN,
philpem@0 72 input JCE1,
philpem@0 73 input [14:0] ER2_TDO,
philpem@0 74 output reg [14:0] IP_ENABLE,
philpem@0 75 input ISPTRACY_ER2_TDO,
philpem@0 76 output ISPTRACY_ENABLE,
philpem@0 77 output CONTROL_DATAN)/* synthesis syn_hier = hard */;
philpem@0 78
philpem@0 79
philpem@0 80 wire controlDataNBit;
philpem@0 81 wire ispTracyEnableBit;
philpem@0 82 wire [3:0] encodedIpEnableBits;
philpem@0 83 wire [9:0] er1TdiBit;
philpem@0 84 wire captureDrER1;
philpem@0 85
philpem@0 86
philpem@0 87 assign JTDO1 = er1TdiBit[0];
philpem@0 88
philpem@0 89 TYPEB BIT0 (.CLK(JTCK),
philpem@0 90 .RESET_N(JRSTN),
philpem@0 91 .CLKEN(JCE1),
philpem@0 92 .TDI(er1TdiBit[1]),
philpem@0 93 .TDO(er1TdiBit[0]),
philpem@0 94 .DATA_IN(1'b0),
philpem@0 95 .CAPTURE_DR(captureDrER1));
philpem@0 96
philpem@0 97 TYPEB BIT1 (.CLK(JTCK),
philpem@0 98 .RESET_N(JRSTN),
philpem@0 99 .CLKEN(JCE1),
philpem@0 100 .TDI(er1TdiBit[2]),
philpem@0 101 .TDO(er1TdiBit[1]),
philpem@0 102 .DATA_IN(1'b0),
philpem@0 103 .CAPTURE_DR(captureDrER1));
philpem@0 104
philpem@0 105 TYPEB BIT2 (.CLK(JTCK),
philpem@0 106 .RESET_N(JRSTN),
philpem@0 107 .CLKEN(JCE1),
philpem@0 108 .TDI(er1TdiBit[3]),
philpem@0 109 .TDO(er1TdiBit[2]),
philpem@0 110 .DATA_IN(1'b1),
philpem@0 111 .CAPTURE_DR(captureDrER1));
philpem@0 112
philpem@0 113 TYPEA BIT3 (.CLK(JTCK),
philpem@0 114 .RESET_N(JRSTN),
philpem@0 115 .CLKEN(JCE1),
philpem@0 116 .TDI(er1TdiBit[4]),
philpem@0 117 .TDO(er1TdiBit[3]),
philpem@0 118 .DATA_OUT(controlDataNBit),
philpem@0 119 .DATA_IN(controlDataNBit),
philpem@0 120 .CAPTURE_DR(captureDrER1),
philpem@0 121 .UPDATE_DR(JUPDATE));
philpem@0 122
philpem@0 123 assign CONTROL_DATAN = controlDataNBit;
philpem@0 124
philpem@0 125 TYPEA BIT4 (.CLK(JTCK),
philpem@0 126 .RESET_N(JRSTN),
philpem@0 127 .CLKEN(JCE1),
philpem@0 128 .TDI(er1TdiBit[5]),
philpem@0 129 .TDO(er1TdiBit[4]),
philpem@0 130 .DATA_OUT(ispTracyEnableBit),
philpem@0 131 .DATA_IN(ispTracyEnableBit),
philpem@0 132 .CAPTURE_DR(captureDrER1),
philpem@0 133 .UPDATE_DR(JUPDATE)
philpem@0 134 );
philpem@0 135
philpem@0 136 assign ISPTRACY_ENABLE = ispTracyEnableBit;
philpem@0 137
philpem@0 138 TYPEA BIT5 (.CLK(JTCK),
philpem@0 139 .RESET_N(JRSTN),
philpem@0 140 .CLKEN(JCE1),
philpem@0 141 .TDI(er1TdiBit[6]),
philpem@0 142 .TDO(er1TdiBit[5]),
philpem@0 143 .DATA_OUT(encodedIpEnableBits[0]),
philpem@0 144 .DATA_IN(encodedIpEnableBits[0]),
philpem@0 145 .CAPTURE_DR(captureDrER1),
philpem@0 146 .UPDATE_DR(JUPDATE));
philpem@0 147
philpem@0 148 TYPEA BIT6 (.CLK(JTCK),
philpem@0 149 .RESET_N(JRSTN),
philpem@0 150 .CLKEN(JCE1),
philpem@0 151 .TDI(er1TdiBit[7]),
philpem@0 152 .TDO(er1TdiBit[6]),
philpem@0 153 .DATA_OUT(encodedIpEnableBits[1]),
philpem@0 154 .DATA_IN(encodedIpEnableBits[1]),
philpem@0 155 .CAPTURE_DR(captureDrER1),
philpem@0 156 .UPDATE_DR(JUPDATE));
philpem@0 157
philpem@0 158 TYPEA BIT7 (.CLK(JTCK),
philpem@0 159 .RESET_N(JRSTN),
philpem@0 160 .CLKEN(JCE1),
philpem@0 161 .TDI(er1TdiBit[8]),
philpem@0 162 .TDO(er1TdiBit[7]),
philpem@0 163 .DATA_OUT(encodedIpEnableBits[2]),
philpem@0 164 .DATA_IN(encodedIpEnableBits[2]),
philpem@0 165 .CAPTURE_DR(captureDrER1),
philpem@0 166 .UPDATE_DR(JUPDATE));
philpem@0 167
philpem@0 168 TYPEA BIT8 (.CLK(JTCK),
philpem@0 169 .RESET_N(JRSTN),
philpem@0 170 .CLKEN(JCE1),
philpem@0 171 .TDI(er1TdiBit[9]),
philpem@0 172 .TDO(er1TdiBit[8]),
philpem@0 173 .DATA_OUT(encodedIpEnableBits[3]),
philpem@0 174 .DATA_IN(encodedIpEnableBits[3]),
philpem@0 175 .CAPTURE_DR(captureDrER1),
philpem@0 176 .UPDATE_DR(JUPDATE)
philpem@0 177 );
philpem@0 178
philpem@0 179 assign er1TdiBit[9] = JTDI;
philpem@0 180 assign captureDrER1 = !JSHIFT & JCE1;
philpem@0 181
philpem@0 182 always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
philpem@0 183 begin
philpem@0 184 case (encodedIpEnableBits)
philpem@0 185 4'h0: begin
philpem@0 186 IP_ENABLE <= 15'b000000000000000;
philpem@0 187 JTDO2 <= ISPTRACY_ER2_TDO;
philpem@0 188 end
philpem@0 189 4'h1: begin
philpem@0 190 IP_ENABLE <= 15'b000000000000001;
philpem@0 191 JTDO2 <= ER2_TDO[0];
philpem@0 192 end
philpem@0 193 4'h2: begin
philpem@0 194 IP_ENABLE <= 15'b000000000000010;
philpem@0 195 JTDO2 <= ER2_TDO[1];
philpem@0 196 end
philpem@0 197 4'h3: begin
philpem@0 198 IP_ENABLE <= 15'b000000000000100;
philpem@0 199 JTDO2 <= ER2_TDO[2];
philpem@0 200 end
philpem@0 201 4'h4: begin
philpem@0 202 IP_ENABLE <= 15'b000000000001000;
philpem@0 203 JTDO2 <= ER2_TDO[3];
philpem@0 204 end
philpem@0 205 4'h5: begin
philpem@0 206 IP_ENABLE <= 15'b000000000010000;
philpem@0 207 JTDO2 <= ER2_TDO[4];
philpem@0 208 end
philpem@0 209 4'h6: begin
philpem@0 210 IP_ENABLE <= 15'b000000000100000;
philpem@0 211 JTDO2 <= ER2_TDO[5];
philpem@0 212 end
philpem@0 213 4'h7: begin
philpem@0 214 IP_ENABLE <= 15'b000000001000000;
philpem@0 215 JTDO2 <= ER2_TDO[6];
philpem@0 216 end
philpem@0 217 4'h8: begin
philpem@0 218 IP_ENABLE <= 15'b000000010000000;
philpem@0 219 JTDO2 <= ER2_TDO[7];
philpem@0 220 end
philpem@0 221 4'h9: begin
philpem@0 222 IP_ENABLE <= 15'b000000100000000;
philpem@0 223 JTDO2 <= ER2_TDO[8];
philpem@0 224 end
philpem@0 225 4'hA: begin
philpem@0 226 IP_ENABLE <= 15'b000001000000000;
philpem@0 227 JTDO2 <= ER2_TDO[9];
philpem@0 228 end
philpem@0 229 4'hB: begin
philpem@0 230 IP_ENABLE <= 15'b000010000000000;
philpem@0 231 JTDO2 <= ER2_TDO[10];
philpem@0 232 end
philpem@0 233 4'hC: begin
philpem@0 234 IP_ENABLE <= 15'b000100000000000;
philpem@0 235 JTDO2 <= ER2_TDO[11];
philpem@0 236 end
philpem@0 237 4'hD: begin
philpem@0 238 IP_ENABLE <= 15'b001000000000000;
philpem@0 239 JTDO2 <= ER2_TDO[12];
philpem@0 240 end
philpem@0 241 4'hE: begin
philpem@0 242 IP_ENABLE <= 15'b010000000000000;
philpem@0 243 JTDO2 <= ER2_TDO[13];
philpem@0 244 end
philpem@0 245 4'hF: begin
philpem@0 246 IP_ENABLE <= 15'b100000000000000;
philpem@0 247 JTDO2 <= ER2_TDO[14];
philpem@0 248 end
philpem@0 249 endcase
philpem@0 250 end
philpem@0 251 endmodule