Sat, 06 Aug 2011 01:26:56 +0100
remove synthesis delay entities to ease merge
philpem@26 | 1 | // ================================================================== |
philpem@26 | 2 | // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< |
philpem@26 | 3 | // ------------------------------------------------------------------ |
philpem@26 | 4 | // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation |
philpem@26 | 5 | // ALL RIGHTS RESERVED |
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philpem@26 | 9 | // |
philpem@26 | 10 | // Permission: |
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philpem@26 | 12 | // Lattice Semiconductor grants permission to use this code |
philpem@26 | 13 | // pursuant to the terms of the Lattice Semiconductor Corporation |
philpem@26 | 14 | // Open Source License Agreement. |
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philpem@26 | 19 | // functionality of this code. It is the user's responsibility to |
philpem@26 | 20 | // verify the user’s design for consistency and functionality through |
philpem@26 | 21 | // the use of formal verification methods. |
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philpem@0 | 37 | // FILE DETAILS |
philpem@0 | 38 | // Project : LatticeMico32 |
philpem@0 | 39 | // File : jtag_cores.v |
philpem@0 | 40 | // Title : Instantiates all IP cores on JTAG chain. |
philpem@0 | 41 | // Dependencies : system_conf.v |
philpem@0 | 42 | // Version : 6.0.14 |
philpem@0 | 43 | // : modified to use jtagconn for LM32, |
philpem@0 | 44 | // : all technologies 7/10/07 |
philpem@0 | 45 | // Version : 7.0SP2, 3.0 |
philpem@0 | 46 | // : No Change |
philpem@0 | 47 | // Version : 3.1 |
philpem@0 | 48 | // : No Change |
philpem@0 | 49 | // ============================================================================ |
philpem@0 | 50 | |
philpem@0 | 51 | `include "system_conf.v" |
philpem@0 | 52 | |
philpem@0 | 53 | ///////////////////////////////////////////////////// |
philpem@0 | 54 | // jtagconn16 Module Definition |
philpem@0 | 55 | ///////////////////////////////////////////////////// |
philpem@0 | 56 | |
philpem@0 | 57 | module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ; |
philpem@0 | 58 | input er2_tdo ; |
philpem@0 | 59 | output jtck ; |
philpem@0 | 60 | output jtdi ; |
philpem@0 | 61 | output jshift ; |
philpem@0 | 62 | output jupdate ; |
philpem@0 | 63 | output jrstn ; |
philpem@0 | 64 | output jce2 ; |
philpem@0 | 65 | output ip_enable ; |
philpem@0 | 66 | endmodule |
philpem@0 | 67 | |
philpem@0 | 68 | ///////////////////////////////////////////////////// |
philpem@0 | 69 | // Module interface |
philpem@0 | 70 | ///////////////////////////////////////////////////// |
philpem@0 | 71 | |
philpem@0 | 72 | (* syn_hier="hard" *) module jtag_cores ( |
philpem@0 | 73 | // ----- Inputs ------- |
philpem@0 | 74 | reg_d, |
philpem@0 | 75 | reg_addr_d, |
philpem@0 | 76 | // ----- Outputs ------- |
philpem@0 | 77 | reg_update, |
philpem@0 | 78 | reg_q, |
philpem@0 | 79 | reg_addr_q, |
philpem@0 | 80 | jtck, |
philpem@0 | 81 | jrstn |
philpem@0 | 82 | ); |
philpem@0 | 83 | |
philpem@0 | 84 | ///////////////////////////////////////////////////// |
philpem@0 | 85 | // Inputs |
philpem@0 | 86 | ///////////////////////////////////////////////////// |
philpem@0 | 87 | |
philpem@0 | 88 | input [7:0] reg_d; |
philpem@0 | 89 | input [2:0] reg_addr_d; |
philpem@0 | 90 | |
philpem@0 | 91 | ///////////////////////////////////////////////////// |
philpem@0 | 92 | // Outputs |
philpem@0 | 93 | ///////////////////////////////////////////////////// |
philpem@0 | 94 | |
philpem@0 | 95 | output reg_update; |
philpem@0 | 96 | wire reg_update; |
philpem@0 | 97 | output [7:0] reg_q; |
philpem@0 | 98 | wire [7:0] reg_q; |
philpem@0 | 99 | output [2:0] reg_addr_q; |
philpem@0 | 100 | wire [2:0] reg_addr_q; |
philpem@0 | 101 | |
philpem@0 | 102 | output jtck; |
philpem@0 | 103 | wire jtck; /* synthesis syn_keep=1 */ |
philpem@0 | 104 | output jrstn; |
philpem@0 | 105 | wire jrstn; /* synthesis syn_keep=1 */ |
philpem@0 | 106 | |
philpem@0 | 107 | ///////////////////////////////////////////////////// |
philpem@0 | 108 | // Instantiations |
philpem@0 | 109 | ///////////////////////////////////////////////////// |
philpem@0 | 110 | |
philpem@0 | 111 | wire jtdi; /* synthesis syn_keep=1 */ |
philpem@0 | 112 | wire er2_tdo2; /* synthesis syn_keep=1 */ |
philpem@0 | 113 | wire jshift; /* synthesis syn_keep=1 */ |
philpem@0 | 114 | wire jupdate; /* synthesis syn_keep=1 */ |
philpem@0 | 115 | wire jce2; /* synthesis syn_keep=1 */ |
philpem@0 | 116 | wire ip_enable; /* synthesis syn_keep=1 */ |
philpem@0 | 117 | |
philpem@0 | 118 | (* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst ( |
philpem@0 | 119 | .er2_tdo (er2_tdo2), |
philpem@0 | 120 | .jtck (jtck), |
philpem@0 | 121 | .jtdi (jtdi), |
philpem@0 | 122 | .jshift (jshift), |
philpem@0 | 123 | .jupdate (jupdate), |
philpem@0 | 124 | .jrstn (jrstn), |
philpem@0 | 125 | .jce2 (jce2), |
philpem@0 | 126 | .ip_enable (ip_enable) |
philpem@0 | 127 | ); |
philpem@0 | 128 | |
philpem@0 | 129 | (* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst ( |
philpem@0 | 130 | .JTCK (jtck), |
philpem@0 | 131 | .JTDI (jtdi), |
philpem@0 | 132 | .JTDO2 (er2_tdo2), |
philpem@0 | 133 | .JSHIFT (jshift), |
philpem@0 | 134 | .JUPDATE (jupdate), |
philpem@0 | 135 | .JRSTN (jrstn), |
philpem@0 | 136 | .JCE2 (jce2), |
philpem@0 | 137 | .JTAGREG_ENABLE (ip_enable), |
philpem@0 | 138 | .CONTROL_DATAN (), |
philpem@0 | 139 | .REG_UPDATE (reg_update), |
philpem@0 | 140 | .REG_D (reg_d), |
philpem@0 | 141 | .REG_ADDR_D (reg_addr_d), |
philpem@0 | 142 | .REG_Q (reg_q), |
philpem@0 | 143 | .REG_ADDR_Q (reg_addr_q) |
philpem@0 | 144 | ); |
philpem@0 | 145 | |
philpem@0 | 146 | endmodule |