jtag_lm32.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
philpem@26 4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
philpem@26 5 // ALL RIGHTS RESERVED
philpem@26 6 // ------------------------------------------------------------------
philpem@26 7 //
philpem@26 8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
philpem@26 9 //
philpem@26 10 // Permission:
philpem@26 11 //
philpem@26 12 // Lattice Semiconductor grants permission to use this code
philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
philpem@26 15 //
philpem@26 16 // Disclaimer:
philpem@0 17 //
philpem@26 18 // Lattice Semiconductor provides no warranty regarding the use or
philpem@26 19 // functionality of this code. It is the user's responsibility to
philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
philpem@26 22 //
philpem@26 23 // --------------------------------------------------------------------
philpem@26 24 //
philpem@26 25 // Lattice Semiconductor Corporation
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philpem@26 29 //
philpem@26 30 // TEL: 1-800-Lattice (USA and Canada)
philpem@26 31 // 503-286-8001 (other locations)
philpem@26 32 //
philpem@26 33 // web: http://www.latticesemi.com/
philpem@26 34 // email: techsupport@latticesemi.com
philpem@26 35 //
philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : jtag_lm32.v
philpem@0 40 // Title : JTAG data register for LM32 CPU debug interface
philpem@0 41 // Version : 6.0.13
philpem@0 42 // : Initial Release
philpem@0 43 // Version : 7.0SP2, 3.0
philpem@0 44 // : No Change
philpem@0 45 // Version : 3.1
philpem@0 46 // : No Change
philpem@0 47 // =============================================================================
philpem@0 48
philpem@0 49 /////////////////////////////////////////////////////
philpem@0 50 // Module interface
philpem@0 51 /////////////////////////////////////////////////////
philpem@0 52
philpem@0 53 module jtag_lm32 (
philpem@0 54 input JTCK,
philpem@0 55 input JTDI,
philpem@0 56 output JTDO2,
philpem@0 57 input JSHIFT,
philpem@0 58 input JUPDATE,
philpem@0 59 input JRSTN,
philpem@0 60 input JCE2,
philpem@0 61 input JTAGREG_ENABLE,
philpem@0 62 input CONTROL_DATAN,
philpem@0 63 output REG_UPDATE,
philpem@0 64 input [7:0] REG_D,
philpem@0 65 input [2:0] REG_ADDR_D,
philpem@0 66 output [7:0] REG_Q,
philpem@0 67 output [2:0] REG_ADDR_Q
philpem@0 68 );
philpem@0 69
philpem@0 70 /////////////////////////////////////////////////////
philpem@0 71 // Internal nets and registers
philpem@0 72 /////////////////////////////////////////////////////
philpem@0 73
philpem@0 74 wire [9:0] tdibus;
philpem@0 75
philpem@0 76 /////////////////////////////////////////////////////
philpem@0 77 // Instantiations
philpem@0 78 /////////////////////////////////////////////////////
philpem@0 79
philpem@0 80 TYPEA DATA_BIT0 (
philpem@0 81 .CLK(JTCK),
philpem@0 82 .RESET_N(JRSTN),
philpem@0 83 .CLKEN(clk_enable),
philpem@0 84 .TDI(JTDI),
philpem@0 85 .TDO(tdibus[0]),
philpem@0 86 .DATA_OUT(REG_Q[0]),
philpem@0 87 .DATA_IN(REG_D[0]),
philpem@0 88 .CAPTURE_DR(captureDr),
philpem@0 89 .UPDATE_DR(JUPDATE)
philpem@0 90 );
philpem@0 91
philpem@0 92 TYPEA DATA_BIT1 (
philpem@0 93 .CLK(JTCK),
philpem@0 94 .RESET_N(JRSTN),
philpem@0 95 .CLKEN(clk_enable),
philpem@0 96 .TDI(tdibus[0]),
philpem@0 97 .TDO(tdibus[1]),
philpem@0 98 .DATA_OUT(REG_Q[1]),
philpem@0 99 .DATA_IN(REG_D[1]),
philpem@0 100 .CAPTURE_DR(captureDr),
philpem@0 101 .UPDATE_DR(JUPDATE)
philpem@0 102 );
philpem@0 103
philpem@0 104 TYPEA DATA_BIT2 (
philpem@0 105 .CLK(JTCK),
philpem@0 106 .RESET_N(JRSTN),
philpem@0 107 .CLKEN(clk_enable),
philpem@0 108 .TDI(tdibus[1]),
philpem@0 109 .TDO(tdibus[2]),
philpem@0 110 .DATA_OUT(REG_Q[2]),
philpem@0 111 .DATA_IN(REG_D[2]),
philpem@0 112 .CAPTURE_DR(captureDr),
philpem@0 113 .UPDATE_DR(JUPDATE)
philpem@0 114 );
philpem@0 115
philpem@0 116 TYPEA DATA_BIT3 (
philpem@0 117 .CLK(JTCK),
philpem@0 118 .RESET_N(JRSTN),
philpem@0 119 .CLKEN(clk_enable),
philpem@0 120 .TDI(tdibus[2]),
philpem@0 121 .TDO(tdibus[3]),
philpem@0 122 .DATA_OUT(REG_Q[3]),
philpem@0 123 .DATA_IN(REG_D[3]),
philpem@0 124 .CAPTURE_DR(captureDr),
philpem@0 125 .UPDATE_DR(JUPDATE)
philpem@0 126 );
philpem@0 127
philpem@0 128 TYPEA DATA_BIT4 (
philpem@0 129 .CLK(JTCK),
philpem@0 130 .RESET_N(JRSTN),
philpem@0 131 .CLKEN(clk_enable),
philpem@0 132 .TDI(tdibus[3]),
philpem@0 133 .TDO(tdibus[4]),
philpem@0 134 .DATA_OUT(REG_Q[4]),
philpem@0 135 .DATA_IN(REG_D[4]),
philpem@0 136 .CAPTURE_DR(captureDr),
philpem@0 137 .UPDATE_DR(JUPDATE)
philpem@0 138 );
philpem@0 139
philpem@0 140 TYPEA DATA_BIT5 (
philpem@0 141 .CLK(JTCK),
philpem@0 142 .RESET_N(JRSTN),
philpem@0 143 .CLKEN(clk_enable),
philpem@0 144 .TDI(tdibus[4]),
philpem@0 145 .TDO(tdibus[5]),
philpem@0 146 .DATA_OUT(REG_Q[5]),
philpem@0 147 .DATA_IN(REG_D[5]),
philpem@0 148 .CAPTURE_DR(captureDr),
philpem@0 149 .UPDATE_DR(JUPDATE)
philpem@0 150 );
philpem@0 151
philpem@0 152 TYPEA DATA_BIT6 (
philpem@0 153 .CLK(JTCK),
philpem@0 154 .RESET_N(JRSTN),
philpem@0 155 .CLKEN(clk_enable),
philpem@0 156 .TDI(tdibus[5]),
philpem@0 157 .TDO(tdibus[6]),
philpem@0 158 .DATA_OUT(REG_Q[6]),
philpem@0 159 .DATA_IN(REG_D[6]),
philpem@0 160 .CAPTURE_DR(captureDr),
philpem@0 161 .UPDATE_DR(JUPDATE)
philpem@0 162 );
philpem@0 163
philpem@0 164 TYPEA DATA_BIT7 (
philpem@0 165 .CLK(JTCK),
philpem@0 166 .RESET_N(JRSTN),
philpem@0 167 .CLKEN(clk_enable),
philpem@0 168 .TDI(tdibus[6]),
philpem@0 169 .TDO(tdibus[7]),
philpem@0 170 .DATA_OUT(REG_Q[7]),
philpem@0 171 .DATA_IN(REG_D[7]),
philpem@0 172 .CAPTURE_DR(captureDr),
philpem@0 173 .UPDATE_DR(JUPDATE)
philpem@0 174 );
philpem@0 175
philpem@0 176 TYPEA ADDR_BIT0 (
philpem@0 177 .CLK(JTCK),
philpem@0 178 .RESET_N(JRSTN),
philpem@0 179 .CLKEN(clk_enable),
philpem@0 180 .TDI(tdibus[7]),
philpem@0 181 .TDO(tdibus[8]),
philpem@0 182 .DATA_OUT(REG_ADDR_Q[0]),
philpem@0 183 .DATA_IN(REG_ADDR_D[0]),
philpem@0 184 .CAPTURE_DR(captureDr),
philpem@0 185 .UPDATE_DR(JUPDATE)
philpem@0 186 );
philpem@0 187
philpem@0 188 TYPEA ADDR_BIT1 (
philpem@0 189 .CLK(JTCK),
philpem@0 190 .RESET_N(JRSTN),
philpem@0 191 .CLKEN(clk_enable),
philpem@0 192 .TDI(tdibus[8]),
philpem@0 193 .TDO(tdibus[9]),
philpem@0 194 .DATA_OUT(REG_ADDR_Q[1]),
philpem@0 195 .DATA_IN(REG_ADDR_D[1]),
philpem@0 196 .CAPTURE_DR(captureDr),
philpem@0 197 .UPDATE_DR(JUPDATE)
philpem@0 198 );
philpem@0 199
philpem@0 200 TYPEA ADDR_BIT2 (
philpem@0 201 .CLK(JTCK),
philpem@0 202 .RESET_N(JRSTN),
philpem@0 203 .CLKEN(clk_enable),
philpem@0 204 .TDI(tdibus[9]),
philpem@0 205 .TDO(JTDO2),
philpem@0 206 .DATA_OUT(REG_ADDR_Q[2]),
philpem@0 207 .DATA_IN(REG_ADDR_D[2]),
philpem@0 208 .CAPTURE_DR(captureDr),
philpem@0 209 .UPDATE_DR(JUPDATE)
philpem@0 210 );
philpem@0 211
philpem@0 212 /////////////////////////////////////////////////////
philpem@0 213 // Combinational logic
philpem@0 214 /////////////////////////////////////////////////////
philpem@0 215
philpem@0 216 assign clk_enable = JTAGREG_ENABLE & JCE2;
philpem@0 217 assign captureDr = !JSHIFT & JCE2;
philpem@0 218 // JCE2 is only active during shift
philpem@0 219 assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
philpem@0 220
philpem@0 221 endmodule