lm32_dcache.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
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philpem@26 11 //
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philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
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philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
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philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : lm32_dcache.v
philpem@0 40 // Title : Data cache
philpem@0 41 // Dependencies : lm32_include.v
philpem@0 42 // Version : 6.1.17
philpem@0 43 // : Initial Release
philpem@0 44 // Version : 7.0SP2, 3.0
philpem@0 45 // : No Change
philpem@0 46 // Version : 3.1
philpem@0 47 // : Support for user-selected resource usage when implementing
philpem@0 48 // : cache memory. Additional parameters must be defined when
philpem@0 49 // : invoking lm32_ram.v
philpem@0 50 // =============================================================================
philpem@0 51
philpem@0 52 `include "lm32_include.v"
philpem@0 53
philpem@0 54 `ifdef CFG_DCACHE_ENABLED
philpem@0 55
philpem@0 56 `define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
philpem@0 57 `define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
philpem@0 58 `define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
philpem@0 59 `define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
philpem@0 60
philpem@0 61 `define LM32_DC_TMEM_ADDR_WIDTH addr_set_width
philpem@0 62 `define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0
philpem@0 63 `define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
philpem@0 64 `define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0
philpem@0 65
philpem@0 66 `define LM32_DC_TAGS_WIDTH (addr_tag_width+1)
philpem@0 67 `define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0
philpem@0 68 `define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1
philpem@0 69 `define LM32_DC_TAGS_VALID_RNG 0
philpem@0 70
philpem@0 71 `define LM32_DC_STATE_RNG 2:0
philpem@0 72 `define LM32_DC_STATE_FLUSH 3'b001
philpem@0 73 `define LM32_DC_STATE_CHECK 3'b010
philpem@0 74 `define LM32_DC_STATE_REFILL 3'b100
philpem@0 75
philpem@0 76 /////////////////////////////////////////////////////
philpem@0 77 // Module interface
philpem@0 78 /////////////////////////////////////////////////////
philpem@0 79
philpem@0 80 module lm32_dcache (
philpem@0 81 // ----- Inputs -----
philpem@0 82 clk_i,
philpem@0 83 rst_i,
philpem@0 84 stall_a,
philpem@0 85 stall_x,
philpem@0 86 stall_m,
philpem@0 87 address_x,
philpem@0 88 address_m,
philpem@0 89 load_q_m,
philpem@0 90 store_q_m,
philpem@0 91 store_data,
philpem@0 92 store_byte_select,
philpem@0 93 refill_ready,
philpem@0 94 refill_data,
philpem@0 95 dflush,
philpem@0 96 // ----- Outputs -----
philpem@0 97 stall_request,
philpem@0 98 restart_request,
philpem@0 99 refill_request,
philpem@0 100 refill_address,
philpem@0 101 refilling,
philpem@0 102 load_data
philpem@0 103 );
philpem@0 104
philpem@0 105 /////////////////////////////////////////////////////
philpem@0 106 // Parameters
philpem@0 107 /////////////////////////////////////////////////////
philpem@0 108
philpem@0 109 parameter associativity = 1; // Associativity of the cache (Number of ways)
philpem@0 110 parameter sets = 512; // Number of sets
philpem@0 111 parameter bytes_per_line = 16; // Number of bytes per cache line
philpem@0 112 parameter base_address = 0; // Base address of cachable memory
philpem@0 113 parameter limit = 0; // Limit (highest address) of cachable memory
philpem@0 114
philpem@0 115 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
philpem@0 116 localparam addr_set_width = clogb2(sets)-1;
philpem@0 117 localparam addr_offset_lsb = 2;
philpem@0 118 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
philpem@0 119 localparam addr_set_lsb = (addr_offset_msb+1);
philpem@0 120 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
philpem@0 121 localparam addr_tag_lsb = (addr_set_msb+1);
philpem@0 122 localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
philpem@0 123 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
philpem@0 124
philpem@0 125 /////////////////////////////////////////////////////
philpem@0 126 // Inputs
philpem@0 127 /////////////////////////////////////////////////////
philpem@0 128
philpem@0 129 input clk_i; // Clock
philpem@0 130 input rst_i; // Reset
philpem@0 131
philpem@0 132 input stall_a; // Stall A stage
philpem@0 133 input stall_x; // Stall X stage
philpem@0 134 input stall_m; // Stall M stage
philpem@0 135
philpem@0 136 input [`LM32_WORD_RNG] address_x; // X stage load/store address
philpem@0 137 input [`LM32_WORD_RNG] address_m; // M stage load/store address
philpem@0 138 input load_q_m; // Load instruction in M stage
philpem@0 139 input store_q_m; // Store instruction in M stage
philpem@0 140 input [`LM32_WORD_RNG] store_data; // Data to store
philpem@0 141 input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified
philpem@0 142
philpem@0 143 input refill_ready; // Indicates next word of refill data is ready
philpem@0 144 input [`LM32_WORD_RNG] refill_data; // Refill data
philpem@0 145
philpem@0 146 input dflush; // Indicates cache should be flushed
philpem@0 147
philpem@0 148 /////////////////////////////////////////////////////
philpem@0 149 // Outputs
philpem@0 150 /////////////////////////////////////////////////////
philpem@0 151
philpem@0 152 output stall_request; // Request pipeline be stalled because cache is busy
philpem@0 153 wire stall_request;
philpem@0 154 output restart_request; // Request to restart instruction that caused the cache miss
philpem@0 155 reg restart_request;
philpem@0 156 output refill_request; // Request a refill
philpem@0 157 reg refill_request;
philpem@0 158 output [`LM32_WORD_RNG] refill_address; // Address to refill from
philpem@0 159 reg [`LM32_WORD_RNG] refill_address;
philpem@0 160 output refilling; // Indicates if the cache is currently refilling
philpem@0 161 reg refilling;
philpem@0 162 output [`LM32_WORD_RNG] load_data; // Data read from cache
philpem@0 163 wire [`LM32_WORD_RNG] load_data;
philpem@0 164
philpem@0 165 /////////////////////////////////////////////////////
philpem@0 166 // Internal nets and registers
philpem@0 167 /////////////////////////////////////////////////////
philpem@0 168
philpem@0 169 wire read_port_enable; // Cache memory read port clock enable
philpem@0 170 wire write_port_enable; // Cache memory write port clock enable
philpem@0 171 wire [0:associativity-1] way_tmem_we; // Tag memory write enable
philpem@0 172 wire [0:associativity-1] way_dmem_we; // Data memory write enable
philpem@0 173 wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory
philpem@0 174 wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
philpem@0 175 wire [0:associativity-1] way_valid; // Indicates which ways are valid
philpem@0 176 wire [0:associativity-1] way_match; // Indicates which ways matched
philpem@0 177 wire miss; // Indicates no ways matched
philpem@0 178
philpem@0 179 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address
philpem@0 180 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
philpem@0 181 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
philpem@0 182 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
philpem@0 183 wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
philpem@0 184 reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
philpem@0 185
philpem@0 186 reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
philpem@0 187 wire flushing; // Indicates if cache is currently flushing
philpem@0 188 wire check; // Indicates if cache is currently checking for hits/misses
philpem@0 189 wire refill; // Indicates if cache is currently refilling
philpem@0 190
philpem@0 191 wire valid_store; // Indicates if there is a valid store instruction
philpem@0 192 reg [associativity-1:0] refill_way_select; // Which way should be refilled
philpem@0 193 reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled
philpem@0 194 wire last_refill; // Indicates when on last cycle of cache refill
philpem@0 195 reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
philpem@0 196
philpem@0 197 genvar i, j;
philpem@0 198
philpem@0 199 /////////////////////////////////////////////////////
philpem@0 200 // Functions
philpem@0 201 /////////////////////////////////////////////////////
philpem@0 202
philpem@0 203 `include "lm32_functions.v"
philpem@0 204
philpem@0 205 /////////////////////////////////////////////////////
philpem@0 206 // Instantiations
philpem@0 207 /////////////////////////////////////////////////////
philpem@0 208
philpem@0 209 generate
philpem@0 210 for (i = 0; i < associativity; i = i + 1)
philpem@0 211 begin : memories
philpem@0 212 // Way data
philpem@0 213 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
philpem@0 214 begin : data_memories
philpem@0 215 lm32_ram
philpem@0 216 #(
philpem@0 217 // ----- Parameters -------
philpem@0 218 .data_width (32),
philpem@0 219 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
philpem@0 220 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
philpem@0 221 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 222 .RAM_TYPE ("RAM_DP_TRUE")
philpem@0 223 `else
philpem@0 224 `ifdef CFG_DCACHE_DAT_USE_SLICE
philpem@0 225 .RAM_IMPLEMENTATION ("SLICE")
philpem@0 226 `else
philpem@0 227 .RAM_IMPLEMENTATION ("AUTO")
philpem@0 228 `endif
philpem@0 229 `endif
philpem@0 230 ) way_0_data_ram
philpem@0 231 (
philpem@0 232 // ----- Inputs -------
philpem@0 233 .read_clk (clk_i),
philpem@0 234 .write_clk (clk_i),
philpem@0 235 .reset (rst_i),
philpem@0 236 .read_address (dmem_read_address),
philpem@0 237 .enable_read (read_port_enable),
philpem@0 238 .write_address (dmem_write_address),
philpem@0 239 .enable_write (write_port_enable),
philpem@0 240 .write_enable (way_dmem_we[i]),
philpem@0 241 .write_data (dmem_write_data),
philpem@0 242 // ----- Outputs -------
philpem@0 243 .read_data (way_data[i])
philpem@0 244 );
philpem@0 245 end
philpem@0 246 else
philpem@0 247 begin
philpem@0 248 for (j = 0; j < 4; j = j + 1)
philpem@0 249 begin : byte_memories
philpem@0 250 lm32_ram
philpem@0 251 #(
philpem@0 252 // ----- Parameters -------
philpem@0 253 .data_width (8),
philpem@0 254 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
philpem@0 255 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
philpem@0 256 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 257 .RAM_TYPE ("RAM_DP_TRUE")
philpem@0 258 `else
philpem@0 259 `ifdef CFG_DCACHE_DAT_USE_SLICE
philpem@0 260 .RAM_IMPLEMENTATION ("SLICE")
philpem@0 261 `else
philpem@0 262 .RAM_IMPLEMENTATION ("AUTO")
philpem@0 263 `endif
philpem@0 264 `endif
philpem@0 265 ) way_0_data_ram
philpem@0 266 (
philpem@0 267 // ----- Inputs -------
philpem@0 268 .read_clk (clk_i),
philpem@0 269 .write_clk (clk_i),
philpem@0 270 .reset (rst_i),
philpem@0 271 .read_address (dmem_read_address),
philpem@0 272 .enable_read (read_port_enable),
philpem@0 273 .write_address (dmem_write_address),
philpem@0 274 .enable_write (write_port_enable),
philpem@0 275 .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
philpem@0 276 .write_data (dmem_write_data[(j+1)*8-1:j*8]),
philpem@0 277 // ----- Outputs -------
philpem@0 278 .read_data (way_data[i][(j+1)*8-1:j*8])
philpem@0 279 );
philpem@0 280 end
philpem@0 281 end
philpem@0 282
philpem@0 283 // Way tags
philpem@0 284 lm32_ram
philpem@0 285 #(
philpem@0 286 // ----- Parameters -------
philpem@0 287 .data_width (`LM32_DC_TAGS_WIDTH),
philpem@0 288 .address_width (`LM32_DC_TMEM_ADDR_WIDTH),
philpem@0 289 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
philpem@0 290 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 291 .RAM_TYPE ("RAM_DP_TRUE")
philpem@0 292 `else
philpem@0 293 `ifdef CFG_DCACHE_DAT_USE_SLICE
philpem@0 294 .RAM_IMPLEMENTATION ("SLICE")
philpem@0 295 `else
philpem@0 296 .RAM_IMPLEMENTATION ("AUTO")
philpem@0 297 `endif
philpem@0 298 `endif
philpem@0 299 ) way_0_tag_ram
philpem@0 300 (
philpem@0 301 // ----- Inputs -------
philpem@0 302 .read_clk (clk_i),
philpem@0 303 .write_clk (clk_i),
philpem@0 304 .reset (rst_i),
philpem@0 305 .read_address (tmem_read_address),
philpem@0 306 .enable_read (read_port_enable),
philpem@0 307 .write_address (tmem_write_address),
philpem@0 308 .enable_write (`TRUE),
philpem@0 309 .write_enable (way_tmem_we[i]),
philpem@0 310 .write_data (tmem_write_data),
philpem@0 311 // ----- Outputs -------
philpem@0 312 .read_data ({way_tag[i], way_valid[i]})
philpem@0 313 );
philpem@0 314 end
philpem@0 315
philpem@0 316 endgenerate
philpem@0 317
philpem@0 318 /////////////////////////////////////////////////////
philpem@0 319 // Combinational logic
philpem@0 320 /////////////////////////////////////////////////////
philpem@0 321
philpem@0 322 // Compute which ways in the cache match the address being read
philpem@0 323 generate
philpem@0 324 for (i = 0; i < associativity; i = i + 1)
philpem@0 325 begin : match
philpem@0 326 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
philpem@0 327 end
philpem@0 328 endgenerate
philpem@0 329
philpem@0 330 // Select data from way that matched the address being read
philpem@0 331 generate
philpem@0 332 if (associativity == 1)
philpem@0 333 begin : data_1
philpem@0 334 assign load_data = way_data[0];
philpem@0 335 end
philpem@0 336 else if (associativity == 2)
philpem@0 337 begin : data_2
philpem@0 338 assign load_data = way_match[0] ? way_data[0] : way_data[1];
philpem@0 339 end
philpem@0 340 endgenerate
philpem@0 341
philpem@0 342 generate
philpem@0 343 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
philpem@0 344 begin
philpem@0 345 // Select data to write to data memories
philpem@0 346 always @(*)
philpem@0 347 begin
philpem@0 348 if (refill == `TRUE)
philpem@0 349 dmem_write_data = refill_data;
philpem@0 350 else
philpem@0 351 begin
philpem@0 352 dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
philpem@0 353 dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
philpem@0 354 dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
philpem@0 355 dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
philpem@0 356 end
philpem@0 357 end
philpem@0 358 end
philpem@0 359 else
philpem@0 360 begin
philpem@0 361 // Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
philpem@0 362 always @(*)
philpem@0 363 begin
philpem@0 364 if (refill == `TRUE)
philpem@0 365 dmem_write_data = refill_data;
philpem@0 366 else
philpem@0 367 dmem_write_data = store_data;
philpem@0 368 end
philpem@0 369 end
philpem@0 370 endgenerate
philpem@0 371
philpem@0 372 // Compute address to use to index into the data memories
philpem@0 373 generate
philpem@0 374 if (bytes_per_line > 4)
philpem@0 375 assign dmem_write_address = (refill == `TRUE)
philpem@0 376 ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
philpem@0 377 : address_m[`LM32_DC_ADDR_IDX_RNG];
philpem@0 378 else
philpem@0 379 assign dmem_write_address = (refill == `TRUE)
philpem@0 380 ? refill_address[`LM32_DC_ADDR_SET_RNG]
philpem@0 381 : address_m[`LM32_DC_ADDR_IDX_RNG];
philpem@0 382 endgenerate
philpem@0 383 assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
philpem@0 384 // Compute address to use to index into the tag memories
philpem@0 385 assign tmem_write_address = (flushing == `TRUE)
philpem@0 386 ? flush_set
philpem@0 387 : refill_address[`LM32_DC_ADDR_SET_RNG];
philpem@0 388 assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
philpem@0 389
philpem@0 390 // Compute signal to indicate when we are on the last refill accesses
philpem@0 391 generate
philpem@0 392 if (bytes_per_line > 4)
philpem@0 393 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
philpem@0 394 else
philpem@0 395 assign last_refill = `TRUE;
philpem@0 396 endgenerate
philpem@0 397
philpem@0 398 // Compute data and tag memory access enable
philpem@0 399 assign read_port_enable = (stall_x == `FALSE);
philpem@0 400 assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
philpem@0 401
philpem@0 402 // Determine when we have a valid store
philpem@0 403 assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
philpem@0 404
philpem@0 405 // Compute data and tag memory write enables
philpem@0 406 generate
philpem@0 407 if (associativity == 1)
philpem@0 408 begin : we_1
philpem@0 409 assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
philpem@0 410 assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
philpem@0 411 end
philpem@0 412 else
philpem@0 413 begin : we_2
philpem@0 414 assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
philpem@0 415 assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
philpem@0 416 assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
philpem@0 417 assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
philpem@0 418 end
philpem@0 419 endgenerate
philpem@0 420
philpem@0 421 // On the last refill cycle set the valid bit, for all other writes it should be cleared
philpem@0 422 assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
philpem@0 423 assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
philpem@0 424
philpem@0 425 // Signals that indicate which state we are in
philpem@0 426 assign flushing = state[0];
philpem@0 427 assign check = state[1];
philpem@0 428 assign refill = state[2];
philpem@0 429
philpem@0 430 assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
philpem@0 431 assign stall_request = (check == `FALSE);
philpem@0 432
philpem@0 433 /////////////////////////////////////////////////////
philpem@0 434 // Sequential logic
philpem@0 435 /////////////////////////////////////////////////////
philpem@0 436
philpem@0 437 // Record way selected for replacement on a cache miss
philpem@0 438 generate
philpem@0 439 if (associativity >= 2)
philpem@0 440 begin : way_select
philpem@0 441 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 442 begin
philpem@0 443 if (rst_i == `TRUE)
philpem@27 444 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
philpem@0 445 else
philpem@0 446 begin
philpem@0 447 if (refill_request == `TRUE)
philpem@27 448 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
philpem@0 449 end
philpem@0 450 end
philpem@0 451 end
philpem@0 452 endgenerate
philpem@0 453
philpem@0 454 // Record whether we are currently refilling
philpem@0 455 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 456 begin
philpem@0 457 if (rst_i == `TRUE)
philpem@27 458 refilling <= `FALSE;
philpem@0 459 else
philpem@27 460 refilling <= refill;
philpem@0 461 end
philpem@0 462
philpem@0 463 // Instruction cache control FSM
philpem@0 464 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 465 begin
philpem@0 466 if (rst_i == `TRUE)
philpem@0 467 begin
philpem@27 468 state <= `LM32_DC_STATE_FLUSH;
philpem@27 469 flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
philpem@27 470 refill_request <= `FALSE;
philpem@27 471 refill_address <= {`LM32_WORD_WIDTH{1'bx}};
philpem@27 472 restart_request <= `FALSE;
philpem@0 473 end
philpem@0 474 else
philpem@0 475 begin
philpem@0 476 case (state)
philpem@0 477
philpem@0 478 // Flush the cache
philpem@0 479 `LM32_DC_STATE_FLUSH:
philpem@0 480 begin
philpem@0 481 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
philpem@27 482 state <= `LM32_DC_STATE_CHECK;
philpem@27 483 flush_set <= flush_set - 1'b1;
philpem@0 484 end
philpem@0 485
philpem@0 486 // Check for cache misses
philpem@0 487 `LM32_DC_STATE_CHECK:
philpem@0 488 begin
philpem@0 489 if (stall_a == `FALSE)
philpem@27 490 restart_request <= `FALSE;
philpem@0 491 if (miss == `TRUE)
philpem@0 492 begin
philpem@27 493 refill_request <= `TRUE;
philpem@27 494 refill_address <= address_m;
philpem@27 495 state <= `LM32_DC_STATE_REFILL;
philpem@0 496 end
philpem@0 497 else if (dflush == `TRUE)
philpem@27 498 state <= `LM32_DC_STATE_FLUSH;
philpem@0 499 end
philpem@0 500
philpem@0 501 // Refill a cache line
philpem@0 502 `LM32_DC_STATE_REFILL:
philpem@0 503 begin
philpem@27 504 refill_request <= `FALSE;
philpem@0 505 if (refill_ready == `TRUE)
philpem@0 506 begin
philpem@0 507 if (last_refill == `TRUE)
philpem@0 508 begin
philpem@27 509 restart_request <= `TRUE;
philpem@27 510 state <= `LM32_DC_STATE_CHECK;
philpem@0 511 end
philpem@0 512 end
philpem@0 513 end
philpem@0 514
philpem@0 515 endcase
philpem@0 516 end
philpem@0 517 end
philpem@0 518
philpem@0 519 generate
philpem@0 520 if (bytes_per_line > 4)
philpem@0 521 begin
philpem@0 522 // Refill offset
philpem@0 523 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 524 begin
philpem@0 525 if (rst_i == `TRUE)
philpem@27 526 refill_offset <= {addr_offset_width{1'b0}};
philpem@0 527 else
philpem@0 528 begin
philpem@0 529 case (state)
philpem@0 530
philpem@0 531 // Check for cache misses
philpem@0 532 `LM32_DC_STATE_CHECK:
philpem@0 533 begin
philpem@0 534 if (miss == `TRUE)
philpem@27 535 refill_offset <= {addr_offset_width{1'b0}};
philpem@0 536 end
philpem@0 537
philpem@0 538 // Refill a cache line
philpem@0 539 `LM32_DC_STATE_REFILL:
philpem@0 540 begin
philpem@0 541 if (refill_ready == `TRUE)
philpem@27 542 refill_offset <= refill_offset + 1'b1;
philpem@0 543 end
philpem@0 544
philpem@0 545 endcase
philpem@0 546 end
philpem@0 547 end
philpem@0 548 end
philpem@0 549 endgenerate
philpem@0 550
philpem@0 551 endmodule
philpem@0 552
philpem@0 553 `endif
philpem@0 554