lm32_icache.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
philpem@26 4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
philpem@26 5 // ALL RIGHTS RESERVED
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philpem@26 7 //
philpem@26 8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
philpem@26 9 //
philpem@26 10 // Permission:
philpem@26 11 //
philpem@26 12 // Lattice Semiconductor grants permission to use this code
philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
philpem@26 15 //
philpem@26 16 // Disclaimer:
philpem@0 17 //
philpem@26 18 // Lattice Semiconductor provides no warranty regarding the use or
philpem@26 19 // functionality of this code. It is the user's responsibility to
philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
philpem@26 22 //
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philpem@26 35 //
philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : lm32_icache.v
philpem@0 40 // Title : Instruction cache
philpem@0 41 // Dependencies : lm32_include.v
philpem@0 42 //
philpem@0 43 // Version 3.5
philpem@0 44 // 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
philpem@0 45 // cause segmentation fault due to incorrect fetches.
philpem@0 46 //
philpem@0 47 // Version 3.1
philpem@0 48 // 1. Feature: Support for user-selected resource usage when implementing
philpem@0 49 // cache memory. Additional parameters must be defined when invoking module
philpem@0 50 // lm32_ram. Instruction cache miss mechanism is dependent on branch
philpem@0 51 // prediction being performed in D stage of pipeline.
philpem@0 52 //
philpem@0 53 // Version 7.0SP2, 3.0
philpem@0 54 // No change
philpem@0 55 // =============================================================================
philpem@0 56
philpem@0 57 `include "lm32_include.v"
philpem@0 58
philpem@0 59 `ifdef CFG_ICACHE_ENABLED
philpem@0 60
philpem@0 61 `define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
philpem@0 62 `define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
philpem@0 63 `define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
philpem@0 64 `define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
philpem@0 65
philpem@0 66 `define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
philpem@0 67 `define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
philpem@0 68 `define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
philpem@0 69 `define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
philpem@0 70
philpem@0 71 `define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
philpem@0 72 `define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
philpem@0 73 `define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
philpem@0 74 `define LM32_IC_TAGS_VALID_RNG 0
philpem@0 75
philpem@0 76 `define LM32_IC_STATE_RNG 3:0
philpem@0 77 `define LM32_IC_STATE_FLUSH_INIT 4'b0001
philpem@0 78 `define LM32_IC_STATE_FLUSH 4'b0010
philpem@0 79 `define LM32_IC_STATE_CHECK 4'b0100
philpem@0 80 `define LM32_IC_STATE_REFILL 4'b1000
philpem@0 81
philpem@0 82 /////////////////////////////////////////////////////
philpem@0 83 // Module interface
philpem@0 84 /////////////////////////////////////////////////////
philpem@0 85
philpem@0 86 module lm32_icache (
philpem@0 87 // ----- Inputs -----
philpem@0 88 clk_i,
philpem@0 89 rst_i,
philpem@0 90 stall_a,
philpem@0 91 stall_f,
philpem@0 92 address_a,
philpem@0 93 address_f,
philpem@0 94 read_enable_f,
philpem@0 95 refill_ready,
philpem@0 96 refill_data,
philpem@0 97 iflush,
philpem@0 98 `ifdef CFG_IROM_ENABLED
philpem@0 99 select_f,
philpem@0 100 `endif
philpem@0 101 valid_d,
philpem@0 102 branch_predict_taken_d,
philpem@0 103 // ----- Outputs -----
philpem@0 104 stall_request,
philpem@0 105 restart_request,
philpem@0 106 refill_request,
philpem@0 107 refill_address,
philpem@0 108 refilling,
philpem@0 109 inst
philpem@0 110 );
philpem@0 111
philpem@0 112 /////////////////////////////////////////////////////
philpem@0 113 // Parameters
philpem@0 114 /////////////////////////////////////////////////////
philpem@0 115
philpem@0 116 parameter associativity = 1; // Associativity of the cache (Number of ways)
philpem@0 117 parameter sets = 512; // Number of sets
philpem@0 118 parameter bytes_per_line = 16; // Number of bytes per cache line
philpem@0 119 parameter base_address = 0; // Base address of cachable memory
philpem@0 120 parameter limit = 0; // Limit (highest address) of cachable memory
philpem@0 121
philpem@0 122 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
philpem@0 123 localparam addr_set_width = clogb2(sets)-1;
philpem@0 124 localparam addr_offset_lsb = 2;
philpem@0 125 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
philpem@0 126 localparam addr_set_lsb = (addr_offset_msb+1);
philpem@0 127 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
philpem@0 128 localparam addr_tag_lsb = (addr_set_msb+1);
philpem@0 129 localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
philpem@0 130 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
philpem@0 131
philpem@0 132 /////////////////////////////////////////////////////
philpem@0 133 // Inputs
philpem@0 134 /////////////////////////////////////////////////////
philpem@0 135
philpem@0 136 input clk_i; // Clock
philpem@0 137 input rst_i; // Reset
philpem@0 138
philpem@0 139 input stall_a; // Stall instruction in A stage
philpem@0 140 input stall_f; // Stall instruction in F stage
philpem@0 141
philpem@0 142 input valid_d; // Valid instruction in D stage
philpem@0 143 input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken
philpem@0 144
philpem@0 145 input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
philpem@0 146 input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
philpem@0 147 input read_enable_f; // Indicates if cache access is valid
philpem@0 148
philpem@0 149 input refill_ready; // Next word of refill data is ready
philpem@0 150 input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
philpem@0 151
philpem@0 152 input iflush; // Flush the cache
philpem@0 153 `ifdef CFG_IROM_ENABLED
philpem@0 154 input select_f; // Instruction in F stage is mapped through instruction cache
philpem@0 155 `endif
philpem@0 156
philpem@0 157 /////////////////////////////////////////////////////
philpem@0 158 // Outputs
philpem@0 159 /////////////////////////////////////////////////////
philpem@0 160
philpem@0 161 output stall_request; // Request to stall the pipeline
philpem@0 162 wire stall_request;
philpem@0 163 output restart_request; // Request to restart instruction that caused the cache miss
philpem@0 164 reg restart_request;
philpem@0 165 output refill_request; // Request to refill a cache line
philpem@0 166 wire refill_request;
philpem@0 167 output [`LM32_PC_RNG] refill_address; // Base address of cache refill
philpem@0 168 reg [`LM32_PC_RNG] refill_address;
philpem@0 169 output refilling; // Indicates the instruction cache is currently refilling
philpem@0 170 reg refilling;
philpem@0 171 output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
philpem@0 172 wire [`LM32_INSTRUCTION_RNG] inst;
philpem@0 173
philpem@0 174 /////////////////////////////////////////////////////
philpem@0 175 // Internal nets and registers
philpem@0 176 /////////////////////////////////////////////////////
philpem@0 177
philpem@0 178 wire enable;
philpem@0 179 wire [0:associativity-1] way_mem_we;
philpem@0 180 wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
philpem@0 181 wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
philpem@0 182 wire [0:associativity-1] way_valid;
philpem@0 183 wire [0:associativity-1] way_match;
philpem@0 184 wire miss;
philpem@0 185
philpem@0 186 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
philpem@0 187 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
philpem@0 188 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
philpem@0 189 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
philpem@0 190 wire [`LM32_IC_TAGS_RNG] tmem_write_data;
philpem@0 191
philpem@0 192 reg [`LM32_IC_STATE_RNG] state;
philpem@0 193 wire flushing;
philpem@0 194 wire check;
philpem@0 195 wire refill;
philpem@0 196
philpem@0 197 reg [associativity-1:0] refill_way_select;
philpem@0 198 reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
philpem@0 199 wire last_refill;
philpem@0 200 reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
philpem@0 201
philpem@0 202 genvar i;
philpem@0 203
philpem@0 204 /////////////////////////////////////////////////////
philpem@0 205 // Functions
philpem@0 206 /////////////////////////////////////////////////////
philpem@0 207
philpem@0 208 `include "lm32_functions.v"
philpem@0 209
philpem@0 210 /////////////////////////////////////////////////////
philpem@0 211 // Instantiations
philpem@0 212 /////////////////////////////////////////////////////
philpem@0 213
philpem@0 214 generate
philpem@0 215 for (i = 0; i < associativity; i = i + 1)
philpem@0 216 begin : memories
philpem@0 217
philpem@0 218 lm32_ram
philpem@0 219 #(
philpem@0 220 // ----- Parameters -------
philpem@0 221 .data_width (32),
philpem@0 222 .address_width (`LM32_IC_DMEM_ADDR_WIDTH),
philpem@0 223 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
philpem@0 224 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 225 .RAM_TYPE ("RAM_DP_TRUE")
philpem@0 226 `else
philpem@0 227 `ifdef CFG_ICACHE_DAT_USE_DP
philpem@0 228 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 229 .RAM_TYPE ("RAM_DP")
philpem@0 230 `else
philpem@0 231 `ifdef CFG_ICACHE_DAT_USE_SLICE
philpem@0 232 .RAM_IMPLEMENTATION ("SLICE")
philpem@0 233 `else
philpem@0 234 .RAM_IMPLEMENTATION ("AUTO")
philpem@0 235 `endif
philpem@0 236 `endif
philpem@0 237 `endif
philpem@0 238 )
philpem@0 239 way_0_data_ram
philpem@0 240 (
philpem@0 241 // ----- Inputs -------
philpem@0 242 .read_clk (clk_i),
philpem@0 243 .write_clk (clk_i),
philpem@0 244 .reset (rst_i),
philpem@0 245 .read_address (dmem_read_address),
philpem@0 246 .enable_read (enable),
philpem@0 247 .write_address (dmem_write_address),
philpem@0 248 .enable_write (`TRUE),
philpem@0 249 .write_enable (way_mem_we[i]),
philpem@0 250 .write_data (refill_data),
philpem@0 251 // ----- Outputs -------
philpem@0 252 .read_data (way_data[i])
philpem@0 253 );
philpem@0 254
philpem@0 255 lm32_ram
philpem@0 256 #(
philpem@0 257 // ----- Parameters -------
philpem@0 258 .data_width (`LM32_IC_TAGS_WIDTH),
philpem@0 259 .address_width (`LM32_IC_TMEM_ADDR_WIDTH),
philpem@0 260 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
philpem@0 261 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 262 .RAM_TYPE ("RAM_DP_TRUE")
philpem@0 263 `else
philpem@0 264 `ifdef CFG_ICACHE_DAT_USE_DP
philpem@0 265 .RAM_IMPLEMENTATION ("EBR"),
philpem@0 266 .RAM_TYPE ("RAM_DP")
philpem@0 267 `else
philpem@0 268 `ifdef CFG_ICACHE_DAT_USE_SLICE
philpem@0 269 .RAM_IMPLEMENTATION ("SLICE")
philpem@0 270 `else
philpem@0 271 .RAM_IMPLEMENTATION ("AUTO")
philpem@0 272 `endif
philpem@0 273 `endif
philpem@0 274 `endif
philpem@0 275 )
philpem@0 276 way_0_tag_ram
philpem@0 277 (
philpem@0 278 // ----- Inputs -------
philpem@0 279 .read_clk (clk_i),
philpem@0 280 .write_clk (clk_i),
philpem@0 281 .reset (rst_i),
philpem@0 282 .read_address (tmem_read_address),
philpem@0 283 .enable_read (enable),
philpem@0 284 .write_address (tmem_write_address),
philpem@0 285 .enable_write (`TRUE),
philpem@0 286 .write_enable (way_mem_we[i] | flushing),
philpem@0 287 .write_data (tmem_write_data),
philpem@0 288 // ----- Outputs -------
philpem@0 289 .read_data ({way_tag[i], way_valid[i]})
philpem@0 290 );
philpem@0 291
philpem@0 292 end
philpem@0 293 endgenerate
philpem@0 294
philpem@0 295 /////////////////////////////////////////////////////
philpem@0 296 // Combinational logic
philpem@0 297 /////////////////////////////////////////////////////
philpem@0 298
philpem@0 299 // Compute which ways in the cache match the address address being read
philpem@0 300 generate
philpem@0 301 for (i = 0; i < associativity; i = i + 1)
philpem@0 302 begin : match
philpem@0 303 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
philpem@0 304 end
philpem@0 305 endgenerate
philpem@0 306
philpem@0 307 // Select data from way that matched the address being read
philpem@0 308 generate
philpem@0 309 if (associativity == 1)
philpem@0 310 begin : inst_1
philpem@0 311 assign inst = way_match[0] ? way_data[0] : 32'b0;
philpem@0 312 end
philpem@0 313 else if (associativity == 2)
philpem@0 314 begin : inst_2
philpem@0 315 assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
philpem@0 316 end
philpem@0 317 endgenerate
philpem@0 318
philpem@0 319 // Compute address to use to index into the data memories
philpem@0 320 generate
philpem@0 321 if (bytes_per_line > 4)
philpem@0 322 assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
philpem@0 323 else
philpem@0 324 assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
philpem@0 325 endgenerate
philpem@0 326
philpem@0 327 assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
philpem@0 328
philpem@0 329 // Compute address to use to index into the tag memories
philpem@0 330 assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
philpem@0 331 assign tmem_write_address = flushing
philpem@0 332 ? flush_set
philpem@0 333 : refill_address[`LM32_IC_ADDR_SET_RNG];
philpem@0 334
philpem@0 335 // Compute signal to indicate when we are on the last refill accesses
philpem@0 336 generate
philpem@0 337 if (bytes_per_line > 4)
philpem@0 338 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
philpem@0 339 else
philpem@0 340 assign last_refill = `TRUE;
philpem@0 341 endgenerate
philpem@0 342
philpem@0 343 // Compute data and tag memory access enable
philpem@0 344 assign enable = (stall_a == `FALSE);
philpem@0 345
philpem@0 346 // Compute data and tag memory write enables
philpem@0 347 generate
philpem@0 348 if (associativity == 1)
philpem@0 349 begin : we_1
philpem@0 350 assign way_mem_we[0] = (refill_ready == `TRUE);
philpem@0 351 end
philpem@0 352 else
philpem@0 353 begin : we_2
philpem@0 354 assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
philpem@0 355 assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
philpem@0 356 end
philpem@0 357 endgenerate
philpem@0 358
philpem@0 359 // On the last refill cycle set the valid bit, for all other writes it should be cleared
philpem@0 360 assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
philpem@0 361 assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
philpem@0 362
philpem@0 363 // Signals that indicate which state we are in
philpem@0 364 assign flushing = |state[1:0];
philpem@0 365 assign check = state[2];
philpem@0 366 assign refill = state[3];
philpem@0 367
philpem@0 368 assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
philpem@0 369 assign stall_request = (check == `FALSE);
philpem@0 370 assign refill_request = (refill == `TRUE);
philpem@0 371
philpem@0 372 /////////////////////////////////////////////////////
philpem@0 373 // Sequential logic
philpem@0 374 /////////////////////////////////////////////////////
philpem@0 375
philpem@0 376 // Record way selected for replacement on a cache miss
philpem@0 377 generate
philpem@0 378 if (associativity >= 2)
philpem@0 379 begin : way_select
philpem@0 380 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 381 begin
philpem@0 382 if (rst_i == `TRUE)
philpem@27 383 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
philpem@0 384 else
philpem@0 385 begin
philpem@0 386 if (miss == `TRUE)
philpem@27 387 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
philpem@0 388 end
philpem@0 389 end
philpem@0 390 end
philpem@0 391 endgenerate
philpem@0 392
philpem@0 393 // Record whether we are refilling
philpem@0 394 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 395 begin
philpem@0 396 if (rst_i == `TRUE)
philpem@27 397 refilling <= `FALSE;
philpem@0 398 else
philpem@27 399 refilling <= refill;
philpem@0 400 end
philpem@0 401
philpem@0 402 // Instruction cache control FSM
philpem@0 403 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 404 begin
philpem@0 405 if (rst_i == `TRUE)
philpem@0 406 begin
philpem@27 407 state <= `LM32_IC_STATE_FLUSH_INIT;
philpem@27 408 flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
philpem@27 409 refill_address <= {`LM32_PC_WIDTH{1'bx}};
philpem@27 410 restart_request <= `FALSE;
philpem@0 411 end
philpem@0 412 else
philpem@0 413 begin
philpem@0 414 case (state)
philpem@0 415
philpem@0 416 // Flush the cache for the first time after reset
philpem@0 417 `LM32_IC_STATE_FLUSH_INIT:
philpem@0 418 begin
philpem@0 419 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
philpem@27 420 state <= `LM32_IC_STATE_CHECK;
philpem@27 421 flush_set <= flush_set - 1'b1;
philpem@0 422 end
philpem@0 423
philpem@0 424 // Flush the cache in response to an write to the ICC CSR
philpem@0 425 `LM32_IC_STATE_FLUSH:
philpem@0 426 begin
philpem@0 427 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
philpem@0 428 `ifdef CFG_IROM_ENABLED
philpem@0 429 if (select_f)
philpem@27 430 state <= `LM32_IC_STATE_REFILL;
philpem@0 431 else
philpem@0 432 `endif
philpem@27 433 state <= `LM32_IC_STATE_CHECK;
philpem@0 434
philpem@27 435 flush_set <= flush_set - 1'b1;
philpem@0 436 end
philpem@0 437
philpem@0 438 // Check for cache misses
philpem@0 439 `LM32_IC_STATE_CHECK:
philpem@0 440 begin
philpem@0 441 if (stall_a == `FALSE)
philpem@27 442 restart_request <= `FALSE;
philpem@0 443 if (iflush == `TRUE)
philpem@0 444 begin
philpem@27 445 refill_address <= address_f;
philpem@27 446 state <= `LM32_IC_STATE_FLUSH;
philpem@0 447 end
philpem@0 448 else if (miss == `TRUE)
philpem@0 449 begin
philpem@27 450 refill_address <= address_f;
philpem@27 451 state <= `LM32_IC_STATE_REFILL;
philpem@0 452 end
philpem@0 453 end
philpem@0 454
philpem@0 455 // Refill a cache line
philpem@0 456 `LM32_IC_STATE_REFILL:
philpem@0 457 begin
philpem@0 458 if (refill_ready == `TRUE)
philpem@0 459 begin
philpem@0 460 if (last_refill == `TRUE)
philpem@0 461 begin
philpem@27 462 restart_request <= `TRUE;
philpem@27 463 state <= `LM32_IC_STATE_CHECK;
philpem@0 464 end
philpem@0 465 end
philpem@0 466 end
philpem@0 467
philpem@0 468 endcase
philpem@0 469 end
philpem@0 470 end
philpem@0 471
philpem@0 472 generate
philpem@0 473 if (bytes_per_line > 4)
philpem@0 474 begin
philpem@0 475 // Refill offset
philpem@0 476 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 477 begin
philpem@0 478 if (rst_i == `TRUE)
philpem@27 479 refill_offset <= {addr_offset_width{1'b0}};
philpem@0 480 else
philpem@0 481 begin
philpem@0 482 case (state)
philpem@0 483
philpem@0 484 // Check for cache misses
philpem@0 485 `LM32_IC_STATE_CHECK:
philpem@0 486 begin
philpem@0 487 if (iflush == `TRUE)
philpem@27 488 refill_offset <= {addr_offset_width{1'b0}};
philpem@0 489 else if (miss == `TRUE)
philpem@27 490 refill_offset <= {addr_offset_width{1'b0}};
philpem@0 491 end
philpem@0 492
philpem@0 493 // Refill a cache line
philpem@0 494 `LM32_IC_STATE_REFILL:
philpem@0 495 begin
philpem@0 496 if (refill_ready == `TRUE)
philpem@27 497 refill_offset <= refill_offset + 1'b1;
philpem@0 498 end
philpem@0 499
philpem@0 500 endcase
philpem@0 501 end
philpem@0 502 end
philpem@0 503 end
philpem@0 504 endgenerate
philpem@0 505
philpem@0 506 endmodule
philpem@0 507
philpem@0 508 `endif
philpem@0 509