lm32_include.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
philpem@26 4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
philpem@26 5 // ALL RIGHTS RESERVED
philpem@26 6 // ------------------------------------------------------------------
philpem@26 7 //
philpem@26 8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
philpem@26 9 //
philpem@26 10 // Permission:
philpem@26 11 //
philpem@26 12 // Lattice Semiconductor grants permission to use this code
philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
philpem@26 15 //
philpem@26 16 // Disclaimer:
philpem@0 17 //
philpem@26 18 // Lattice Semiconductor provides no warranty regarding the use or
philpem@26 19 // functionality of this code. It is the user's responsibility to
philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
philpem@26 22 //
philpem@26 23 // --------------------------------------------------------------------
philpem@26 24 //
philpem@26 25 // Lattice Semiconductor Corporation
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philpem@26 30 // TEL: 1-800-Lattice (USA and Canada)
philpem@26 31 // 503-286-8001 (other locations)
philpem@26 32 //
philpem@26 33 // web: http://www.latticesemi.com/
philpem@26 34 // email: techsupport@latticesemi.com
philpem@26 35 //
philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : lm32_include.v
philpem@0 40 // Title : CPU global macros
philpem@0 41 // Version : 6.1.17
philpem@0 42 // : Initial Release
philpem@0 43 // Version : 7.0SP2, 3.0
philpem@0 44 // : No Change
philpem@0 45 // Version : 3.1
philpem@0 46 // : No Change
philpem@0 47 // Version : 3.2
philpem@0 48 // : No Change
philpem@0 49 // Version : 3.3
philpem@0 50 // : Support for extended configuration register
philpem@0 51 // =============================================================================
philpem@0 52
philpem@0 53 `ifdef LM32_INCLUDE_V
philpem@0 54 `else
philpem@0 55 `define LM32_INCLUDE_V
philpem@0 56
philpem@0 57 // Configuration options
philpem@0 58 `include "system_conf.v"
philpem@0 59
philpem@0 60 `ifdef TRUE
philpem@0 61 `else
philpem@0 62 `define TRUE 1'b1
philpem@0 63 `define FALSE 1'b0
philpem@0 64 `define TRUE_N 1'b0
philpem@0 65 `define FALSE_N 1'b1
philpem@0 66 `endif
philpem@0 67
philpem@0 68 // Wishbone configuration
philpem@0 69 `define CFG_IWB_ENABLED
philpem@0 70 `define CFG_DWB_ENABLED
philpem@0 71
philpem@0 72 // Data-path width
philpem@0 73 `define LM32_WORD_WIDTH 32
philpem@0 74 `define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
philpem@0 75 `define LM32_SHIFT_WIDTH 5
philpem@0 76 `define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
philpem@0 77 `define LM32_BYTE_SELECT_WIDTH 4
philpem@0 78 `define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
philpem@0 79
philpem@0 80 // Register file size
philpem@0 81 `define LM32_REGISTERS 32
philpem@0 82 `define LM32_REG_IDX_WIDTH 5
philpem@0 83 `define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
philpem@0 84
philpem@0 85 // Standard register numbers
philpem@0 86 `define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
philpem@0 87 `define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
philpem@0 88 `define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
philpem@0 89
philpem@0 90 // Range of Program Counter. Two LSBs are always 0.
philpem@0 91 // `ifdef CFG_ICACHE_ENABLED
philpem@0 92 // `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
philpem@0 93 // `else
philpem@0 94 // `ifdef CFG_IWB_ENABLED
philpem@0 95 `define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
philpem@0 96 // `else
philpem@0 97 // `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH
philpem@0 98 // `endif
philpem@0 99 // `endif
philpem@0 100 `define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
philpem@0 101
philpem@0 102 // Range of an instruction
philpem@0 103 `define LM32_INSTRUCTION_WIDTH 32
philpem@0 104 `define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
philpem@0 105
philpem@0 106 // Adder operation
philpem@0 107 `define LM32_ADDER_OP_ADD 1'b0
philpem@0 108 `define LM32_ADDER_OP_SUBTRACT 1'b1
philpem@0 109
philpem@0 110 // Shift direction
philpem@0 111 `define LM32_SHIFT_OP_RIGHT 1'b0
philpem@0 112 `define LM32_SHIFT_OP_LEFT 1'b1
philpem@0 113
philpem@0 114 // Currently always enabled
philpem@0 115 `define CFG_BUS_ERRORS_ENABLED
philpem@0 116
philpem@0 117 // Derive macro that indicates whether we have single-stepping or not
philpem@0 118 `ifdef CFG_ROM_DEBUG_ENABLED
philpem@0 119 `define LM32_SINGLE_STEP_ENABLED
philpem@0 120 `else
philpem@0 121 `ifdef CFG_HW_DEBUG_ENABLED
philpem@0 122 `define LM32_SINGLE_STEP_ENABLED
philpem@0 123 `endif
philpem@0 124 `endif
philpem@0 125
philpem@0 126 // Derive macro that indicates whether JTAG interface is required
philpem@0 127 `ifdef CFG_JTAG_UART_ENABLED
philpem@0 128 `define LM32_JTAG_ENABLED
philpem@0 129 `else
philpem@0 130 `ifdef CFG_DEBUG_ENABLED
philpem@0 131 `define LM32_JTAG_ENABLED
philpem@0 132 `else
philpem@0 133 `endif
philpem@0 134 `endif
philpem@0 135
philpem@0 136 // Derive macro that indicates whether we have a barrel-shifter or not
philpem@0 137 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
philpem@0 138 `define LM32_BARREL_SHIFT_ENABLED
philpem@0 139 `else // CFG_PL_BARREL_SHIFT_ENABLED
philpem@0 140 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
philpem@0 141 `define LM32_BARREL_SHIFT_ENABLED
philpem@0 142 `else
philpem@0 143 `define LM32_NO_BARREL_SHIFT
philpem@0 144 `endif
philpem@0 145 `endif // CFG_PL_BARREL_SHIFT_ENABLED
philpem@0 146
philpem@0 147 // Derive macro that indicates whether we have a multiplier or not
philpem@0 148 `ifdef CFG_PL_MULTIPLY_ENABLED
philpem@0 149 `define LM32_MULTIPLY_ENABLED
philpem@0 150 `else
philpem@0 151 `ifdef CFG_MC_MULTIPLY_ENABLED
philpem@0 152 `define LM32_MULTIPLY_ENABLED
philpem@0 153 `endif
philpem@0 154 `endif
philpem@0 155
philpem@0 156 // Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
philpem@0 157 `ifdef CFG_MC_DIVIDE_ENABLED
philpem@0 158 `define LM32_MC_ARITHMETIC_ENABLED
philpem@0 159 `endif
philpem@0 160 `ifdef CFG_MC_MULTIPLY_ENABLED
philpem@0 161 `define LM32_MC_ARITHMETIC_ENABLED
philpem@0 162 `endif
philpem@0 163 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
philpem@0 164 `define LM32_MC_ARITHMETIC_ENABLED
philpem@0 165 `endif
philpem@0 166
philpem@0 167 // Derive macro that indicates if we are using an EBR register file
philpem@0 168 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
philpem@0 169 `define LM32_EBR_REGISTER_FILE
philpem@0 170 `endif
philpem@0 171 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
philpem@0 172 `define LM32_EBR_REGISTER_FILE
philpem@0 173 `endif
philpem@0 174
philpem@0 175 // Revision number
philpem@0 176 `define LM32_REVISION 6'h02
philpem@0 177
philpem@0 178 // Logical operations - Function encoded directly in instruction
philpem@0 179 `define LM32_LOGIC_OP_RNG 3:0
philpem@0 180
philpem@0 181 // Conditions for conditional branches
philpem@0 182 `define LM32_CONDITION_WIDTH 3
philpem@0 183 `define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
philpem@0 184 `define LM32_CONDITION_E 3'b001
philpem@0 185 `define LM32_CONDITION_G 3'b010
philpem@0 186 `define LM32_CONDITION_GE 3'b011
philpem@0 187 `define LM32_CONDITION_GEU 3'b100
philpem@0 188 `define LM32_CONDITION_GU 3'b101
philpem@0 189 `define LM32_CONDITION_NE 3'b111
philpem@0 190 `define LM32_CONDITION_U1 3'b000
philpem@0 191 `define LM32_CONDITION_U2 3'b110
philpem@0 192
philpem@0 193 // Size of load or store instruction - Encoding corresponds to opcode
philpem@0 194 `define LM32_SIZE_WIDTH 2
philpem@0 195 `define LM32_SIZE_RNG 1:0
philpem@0 196 `define LM32_SIZE_BYTE 2'b00
philpem@0 197 `define LM32_SIZE_HWORD 2'b11
philpem@0 198 `define LM32_SIZE_WORD 2'b10
philpem@0 199 `define LM32_ADDRESS_LSBS_WIDTH 2
philpem@0 200
philpem@0 201 // Width and range of a CSR index
philpem@0 202 `ifdef CFG_DEBUG_ENABLED
philpem@0 203 `define LM32_CSR_WIDTH 5
philpem@0 204 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
philpem@0 205 `else
philpem@0 206 `ifdef CFG_JTAG_ENABLED
philpem@0 207 `define LM32_CSR_WIDTH 4
philpem@0 208 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
philpem@0 209 `else
philpem@0 210 `define LM32_CSR_WIDTH 3
philpem@0 211 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
philpem@0 212 `endif
philpem@0 213 `endif
philpem@0 214
philpem@0 215 // CSR indices
philpem@0 216 `define LM32_CSR_IE `LM32_CSR_WIDTH'h0
philpem@0 217 `define LM32_CSR_IM `LM32_CSR_WIDTH'h1
philpem@0 218 `define LM32_CSR_IP `LM32_CSR_WIDTH'h2
philpem@0 219 `define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
philpem@0 220 `define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
philpem@0 221 `define LM32_CSR_CC `LM32_CSR_WIDTH'h5
philpem@0 222 `define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
philpem@0 223 `define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
philpem@0 224 `ifdef CFG_DEBUG_ENABLED
philpem@0 225 `define LM32_CSR_DC `LM32_CSR_WIDTH'h8
philpem@0 226 `define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
philpem@0 227 `endif
philpem@0 228 `define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha
philpem@0 229 `ifdef CFG_JTAG_ENABLED
philpem@0 230 `define LM32_CSR_JTX `LM32_CSR_WIDTH'he
philpem@0 231 `define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
philpem@0 232 `endif
philpem@0 233 `ifdef CFG_DEBUG_ENABLED
philpem@0 234 `define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
philpem@0 235 `define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
philpem@0 236 `define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
philpem@0 237 `define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
philpem@0 238 `define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
philpem@0 239 `define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
philpem@0 240 `define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
philpem@0 241 `define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
philpem@0 242 `endif
philpem@0 243
philpem@0 244 // Values for WPC CSR
philpem@0 245 `define LM32_WPC_C_RNG 1:0
philpem@0 246 `define LM32_WPC_C_DISABLED 2'b00
philpem@0 247 `define LM32_WPC_C_READ 2'b01
philpem@0 248 `define LM32_WPC_C_WRITE 2'b10
philpem@0 249 `define LM32_WPC_C_READ_WRITE 2'b11
philpem@0 250
philpem@0 251 // Exception IDs
philpem@0 252 `define LM32_EID_WIDTH 3
philpem@0 253 `define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
philpem@0 254 `define LM32_EID_RESET 3'h0
philpem@0 255 `define LM32_EID_BREAKPOINT 3'd1
philpem@0 256 `define LM32_EID_INST_BUS_ERROR 3'h2
philpem@0 257 `define LM32_EID_WATCHPOINT 3'd3
philpem@0 258 `define LM32_EID_DATA_BUS_ERROR 3'h4
philpem@0 259 `define LM32_EID_DIVIDE_BY_ZERO 3'h5
philpem@0 260 `define LM32_EID_INTERRUPT 3'h6
philpem@0 261 `define LM32_EID_SCALL 3'h7
philpem@0 262
philpem@0 263 // Pipeline result selection mux controls
philpem@0 264
philpem@0 265 `define LM32_D_RESULT_SEL_0_RNG 0:0
philpem@0 266 `define LM32_D_RESULT_SEL_0_REG_0 1'b0
philpem@0 267 `define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
philpem@0 268
philpem@0 269 `define LM32_D_RESULT_SEL_1_RNG 1:0
philpem@0 270 `define LM32_D_RESULT_SEL_1_ZERO 2'b00
philpem@0 271 `define LM32_D_RESULT_SEL_1_REG_1 2'b01
philpem@0 272 `define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
philpem@0 273
philpem@0 274 `define LM32_USER_OPCODE_WIDTH 11
philpem@0 275 `define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
philpem@0 276
philpem@0 277 // Derive a macro to indicate if either of the caches are implemented
philpem@0 278 `ifdef CFG_ICACHE_ENABLED
philpem@0 279 `define LM32_CACHE_ENABLED
philpem@0 280 `else
philpem@0 281 `ifdef CFG_DCACHE_ENABLED
philpem@0 282 `define LM32_CACHE_ENABLED
philpem@0 283 `endif
philpem@0 284 `endif
philpem@0 285
philpem@0 286 /////////////////////////////////////////////////////
philpem@0 287 // Interrupts
philpem@0 288 /////////////////////////////////////////////////////
philpem@0 289
philpem@0 290 // Always enable interrupts
philpem@0 291 `define CFG_INTERRUPTS_ENABLED
philpem@0 292
philpem@0 293 // Currently this is fixed to 32 and should not be changed
philpem@0 294 `define CFG_INTERRUPTS 32
philpem@0 295 `define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
philpem@0 296 `define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
philpem@0 297
philpem@0 298 /////////////////////////////////////////////////////
philpem@0 299 // General
philpem@0 300 /////////////////////////////////////////////////////
philpem@0 301
philpem@0 302 // Sub-word range types
philpem@0 303 `define LM32_BYTE_WIDTH 8
philpem@0 304 `define LM32_BYTE_RNG 7:0
philpem@0 305 `define LM32_HWORD_WIDTH 16
philpem@0 306 `define LM32_HWORD_RNG 15:0
philpem@0 307
philpem@0 308 // Word sub-byte indicies
philpem@0 309 `define LM32_BYTE_0_RNG 7:0
philpem@0 310 `define LM32_BYTE_1_RNG 15:8
philpem@0 311 `define LM32_BYTE_2_RNG 23:16
philpem@0 312 `define LM32_BYTE_3_RNG 31:24
philpem@0 313
philpem@0 314 // Word sub-halfword indices
philpem@0 315 `define LM32_HWORD_0_RNG 15:0
philpem@0 316 `define LM32_HWORD_1_RNG 31:16
philpem@0 317
philpem@0 318 // Use an asynchronous reset
philpem@0 319 // To use a synchronous reset, define this macro as nothing
philpem@22 320 `define CFG_RESET_SENSITIVITY or posedge rst_i
philpem@0 321
philpem@0 322 // V.T. Srce
philpem@0 323 `define SRCE
philpem@0 324
philpem@0 325 // Whether to include context registers for debug exceptions
philpem@0 326 // in addition to standard exception handling registers
philpem@0 327 // Bizarre - Removing this increases LUT count!
philpem@0 328 `define CFG_DEBUG_EXCEPTIONS_ENABLED
philpem@0 329
philpem@0 330 // Wishbone defines
philpem@0 331 // Refer to Wishbone System-on-Chip Interconnection Architecture
philpem@0 332 // These should probably be moved to a Wishbone common file
philpem@0 333
philpem@0 334 // Wishbone cycle types
philpem@0 335 `define LM32_CTYPE_WIDTH 3
philpem@0 336 `define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
philpem@0 337 `define LM32_CTYPE_CLASSIC 3'b000
philpem@0 338 `define LM32_CTYPE_CONSTANT 3'b001
philpem@0 339 `define LM32_CTYPE_INCREMENTING 3'b010
philpem@0 340 `define LM32_CTYPE_END 3'b111
philpem@0 341
philpem@0 342 // Wishbone burst types
philpem@0 343 `define LM32_BTYPE_WIDTH 2
philpem@0 344 `define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
philpem@0 345 `define LM32_BTYPE_LINEAR 2'b00
philpem@0 346 `define LM32_BTYPE_4_BEAT 2'b01
philpem@0 347 `define LM32_BTYPE_8_BEAT 2'b10
philpem@0 348 `define LM32_BTYPE_16_BEAT 2'b11
philpem@0 349
philpem@0 350 `endif