lm32_logic_op.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
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philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
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philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : lm32_logic_op.v
philpem@0 40 // Title : Logic operations (and / or / not etc)
philpem@0 41 // Dependencies : lm32_include.v
philpem@0 42 // Version : 6.1.17
philpem@0 43 // : Initial Release
philpem@0 44 // Version : 7.0SP2, 3.0
philpem@0 45 // : No Change
philpem@0 46 // Version : 3.1
philpem@0 47 // : No Change
philpem@0 48 // =============================================================================
philpem@0 49
philpem@0 50 `include "lm32_include.v"
philpem@0 51
philpem@0 52 /////////////////////////////////////////////////////
philpem@0 53 // Module interface
philpem@0 54 /////////////////////////////////////////////////////
philpem@0 55
philpem@0 56 module lm32_logic_op (
philpem@0 57 // ----- Inputs -------
philpem@0 58 logic_op_x,
philpem@0 59 operand_0_x,
philpem@0 60 operand_1_x,
philpem@0 61 // ----- Outputs -------
philpem@0 62 logic_result_x
philpem@0 63 );
philpem@0 64
philpem@0 65 /////////////////////////////////////////////////////
philpem@0 66 // Inputs
philpem@0 67 /////////////////////////////////////////////////////
philpem@0 68
philpem@0 69 input [`LM32_LOGIC_OP_RNG] logic_op_x;
philpem@0 70 input [`LM32_WORD_RNG] operand_0_x;
philpem@0 71 input [`LM32_WORD_RNG] operand_1_x;
philpem@0 72
philpem@0 73 /////////////////////////////////////////////////////
philpem@0 74 // Outputs
philpem@0 75 /////////////////////////////////////////////////////
philpem@0 76
philpem@0 77 output [`LM32_WORD_RNG] logic_result_x;
philpem@0 78 reg [`LM32_WORD_RNG] logic_result_x;
philpem@0 79
philpem@0 80 /////////////////////////////////////////////////////
philpem@0 81 // Internal nets and registers
philpem@0 82 /////////////////////////////////////////////////////
philpem@0 83
philpem@0 84 integer logic_idx;
philpem@0 85
philpem@0 86 /////////////////////////////////////////////////////
philpem@0 87 // Combinational Logic
philpem@0 88 /////////////////////////////////////////////////////
philpem@0 89
philpem@0 90 always @(*)
philpem@0 91 begin
philpem@0 92 for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
philpem@0 93 logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
philpem@0 94 end
philpem@0 95
philpem@0 96 endmodule
philpem@0 97