lm32_monitor.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
philpem@26 4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
philpem@26 5 // ALL RIGHTS RESERVED
philpem@26 6 // ------------------------------------------------------------------
philpem@26 7 //
philpem@26 8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
philpem@26 9 //
philpem@26 10 // Permission:
philpem@26 11 //
philpem@26 12 // Lattice Semiconductor grants permission to use this code
philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
philpem@26 15 //
philpem@26 16 // Disclaimer:
philpem@0 17 //
philpem@26 18 // Lattice Semiconductor provides no warranty regarding the use or
philpem@26 19 // functionality of this code. It is the user's responsibility to
philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
philpem@26 22 //
philpem@26 23 // --------------------------------------------------------------------
philpem@26 24 //
philpem@26 25 // Lattice Semiconductor Corporation
philpem@26 26 // 5555 NE Moore Court
philpem@26 27 // Hillsboro, OR 97214
philpem@26 28 // U.S.A
philpem@26 29 //
philpem@26 30 // TEL: 1-800-Lattice (USA and Canada)
philpem@26 31 // 503-286-8001 (other locations)
philpem@26 32 //
philpem@26 33 // web: http://www.latticesemi.com/
philpem@26 34 // email: techsupport@latticesemi.com
philpem@26 35 //
philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : lm32_monitor.v
philpem@0 40 // Title : Debug monitor memory Wishbone interface
philpem@0 41 // Version : 6.1.17
philpem@0 42 // : Initial Release
philpem@0 43 // Version : 7.0SP2, 3.0
philpem@0 44 // : No Change
philpem@0 45 // Version : 3.3
philpem@0 46 // : Removed port mismatch in instantiation of module
philpem@0 47 // : lm32_monitor_ram.
philpem@0 48 // =============================================================================
philpem@0 49
philpem@0 50 `include "system_conf.v"
philpem@0 51 `include "lm32_include.v"
philpem@0 52
philpem@0 53 /////////////////////////////////////////////////////
philpem@0 54 // Module interface
philpem@0 55 /////////////////////////////////////////////////////
philpem@0 56
philpem@0 57 module lm32_monitor (
philpem@0 58 // ----- Inputs -------
philpem@0 59 clk_i,
philpem@0 60 rst_i,
philpem@0 61 MON_ADR_I,
philpem@0 62 MON_CYC_I,
philpem@0 63 MON_DAT_I,
philpem@0 64 MON_SEL_I,
philpem@0 65 MON_STB_I,
philpem@0 66 MON_WE_I,
philpem@0 67 // ----- Outputs -------
philpem@0 68 MON_ACK_O,
philpem@0 69 MON_RTY_O,
philpem@0 70 MON_DAT_O,
philpem@0 71 MON_ERR_O
philpem@0 72 );
philpem@0 73
philpem@0 74 /////////////////////////////////////////////////////
philpem@0 75 // Inputs
philpem@0 76 /////////////////////////////////////////////////////
philpem@0 77
philpem@0 78 input clk_i; // Wishbone clock
philpem@0 79 input rst_i; // Wishbone reset
philpem@8 80 input [10:2] MON_ADR_I; // Wishbone address
philpem@0 81 input MON_STB_I; // Wishbone strobe
philpem@0 82 input MON_CYC_I; // Wishbone cycle
philpem@0 83 input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data
philpem@0 84 input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select
philpem@0 85 input MON_WE_I; // Wishbone write enable
philpem@0 86
philpem@0 87 /////////////////////////////////////////////////////
philpem@0 88 // Outputs
philpem@0 89 /////////////////////////////////////////////////////
philpem@0 90
philpem@0 91 output MON_ACK_O; // Wishbone acknowlege
philpem@0 92 reg MON_ACK_O;
philpem@0 93 output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output
philpem@0 94 reg [`LM32_WORD_RNG] MON_DAT_O;
philpem@0 95 output MON_RTY_O; // Wishbone retry
philpem@0 96 wire MON_RTY_O;
philpem@0 97 output MON_ERR_O; // Wishbone error
philpem@0 98 wire MON_ERR_O;
philpem@0 99
philpem@0 100 /////////////////////////////////////////////////////
philpem@0 101 // Internal nets and registers
philpem@0 102 /////////////////////////////////////////////////////
philpem@0 103
philpem@0 104 reg [1:0] state; // Current state of FSM
philpem@0 105 wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM
philpem@0 106 reg write_enable; // RAM write enable
philpem@0 107 reg [`LM32_WORD_RNG] write_data; // RAM write data
philpem@0 108
philpem@0 109 /////////////////////////////////////////////////////
philpem@0 110 // Instantiations
philpem@0 111 /////////////////////////////////////////////////////
philpem@0 112
philpem@0 113 lm32_monitor_ram ram (
philpem@0 114 // ----- Inputs -------
philpem@0 115 .ClockA (clk_i),
philpem@0 116 .ClockB (clk_i),
philpem@0 117 .ResetA (rst_i),
philpem@0 118 .ResetB (rst_i),
philpem@0 119 .ClockEnA (`TRUE),
philpem@0 120 .ClockEnB (`FALSE),
philpem@0 121 .AddressA (MON_ADR_I[10:2]),
philpem@0 122 .AddressB (9'b0),
philpem@0 123 .DataInA (write_data),
philpem@0 124 .DataInB (32'b0),
philpem@0 125 .WrA (write_enable),
philpem@0 126 .WrB (`FALSE),
philpem@0 127 // ----- Outputs -------
philpem@0 128 .QA (data),
philpem@0 129 .QB (dataB)
philpem@0 130 );
philpem@0 131
philpem@0 132 /////////////////////////////////////////////////////
philpem@0 133 // Combinational Logic
philpem@0 134 /////////////////////////////////////////////////////
philpem@0 135
philpem@0 136 assign MON_RTY_O = `FALSE;
philpem@0 137 assign MON_ERR_O = `FALSE;
philpem@0 138
philpem@0 139 /////////////////////////////////////////////////////
philpem@0 140 // Sequential Logic
philpem@0 141 /////////////////////////////////////////////////////
philpem@0 142
philpem@0 143 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
philpem@0 144 begin
philpem@0 145 if (rst_i == `TRUE)
philpem@0 146 begin
philpem@27 147 write_enable <= `FALSE;
philpem@27 148 MON_ACK_O <= `FALSE;
philpem@27 149 MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
philpem@27 150 state <= 2'b00;
philpem@0 151 end
philpem@0 152 else
philpem@0 153 begin
philpem@22 154 casez (state)
philpem@0 155 2'b01:
philpem@0 156 begin
philpem@0 157 // Output read data to Wishbone
philpem@27 158 MON_ACK_O <= `TRUE;
philpem@27 159 MON_DAT_O <= data;
philpem@0 160 // Sub-word writes are performed using read-modify-write
philpem@0 161 // as the Lattice EBRs don't support byte enables
philpem@0 162 if (MON_WE_I == `TRUE)
philpem@27 163 write_enable <= `TRUE;
philpem@27 164 write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
philpem@27 165 write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
philpem@27 166 write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
philpem@27 167 write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
philpem@27 168 state <= 2'b10;
philpem@0 169 end
philpem@0 170 2'b10:
philpem@0 171 begin
philpem@0 172 // Wishbone access occurs in this cycle
philpem@27 173 write_enable <= `FALSE;
philpem@27 174 MON_ACK_O <= `FALSE;
philpem@27 175 MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
philpem@27 176 state <= 2'b00;
philpem@0 177 end
philpem@22 178 default:
philpem@22 179 begin
philpem@27 180 write_enable <= `FALSE;
philpem@27 181 MON_ACK_O <= `FALSE;
philpem@22 182 // Wait for a Wishbone access
philpem@22 183 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
philpem@27 184 state <= 2'b01;
philpem@22 185 end
philpem@0 186 endcase
philpem@0 187 end
philpem@0 188 end
philpem@0 189
philpem@0 190 endmodule