lm32_top.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
philpem@26 4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
philpem@26 5 // ALL RIGHTS RESERVED
philpem@26 6 // ------------------------------------------------------------------
philpem@26 7 //
philpem@26 8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
philpem@26 9 //
philpem@26 10 // Permission:
philpem@26 11 //
philpem@26 12 // Lattice Semiconductor grants permission to use this code
philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
philpem@26 15 //
philpem@26 16 // Disclaimer:
philpem@0 17 //
philpem@26 18 // Lattice Semiconductor provides no warranty regarding the use or
philpem@26 19 // functionality of this code. It is the user's responsibility to
philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
philpem@26 22 //
philpem@26 23 // --------------------------------------------------------------------
philpem@26 24 //
philpem@26 25 // Lattice Semiconductor Corporation
philpem@26 26 // 5555 NE Moore Court
philpem@26 27 // Hillsboro, OR 97214
philpem@26 28 // U.S.A
philpem@26 29 //
philpem@26 30 // TEL: 1-800-Lattice (USA and Canada)
philpem@26 31 // 503-286-8001 (other locations)
philpem@26 32 //
philpem@26 33 // web: http://www.latticesemi.com/
philpem@26 34 // email: techsupport@latticesemi.com
philpem@26 35 //
philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : lm32_top.v
philpem@0 40 // Title : Top-level of CPU.
philpem@0 41 // Dependencies : lm32_include.v
philpem@0 42 // Version : 6.1.17
philpem@0 43 // : removed SPI - 04/12/07
philpem@0 44 // Version : 7.0SP2, 3.0
philpem@0 45 // : No Change
philpem@0 46 // Version : 3.1
philpem@0 47 // : No Change
philpem@0 48 // =============================================================================
philpem@0 49
philpem@0 50 `include "lm32_include.v"
philpem@0 51
philpem@0 52 /////////////////////////////////////////////////////
philpem@0 53 // Module interface
philpem@0 54 /////////////////////////////////////////////////////
philpem@0 55
philpem@0 56 module lm32_top (
philpem@0 57 // ----- Inputs -------
philpem@0 58 clk_i,
philpem@0 59 rst_i,
philpem@26 60 `ifdef CFG_DEBUG_ENABLED
philpem@26 61 `ifdef CFG_ALTERNATE_EBA
philpem@26 62 at_debug,
philpem@26 63 `endif
philpem@26 64 `endif
philpem@0 65 // From external devices
philpem@0 66 `ifdef CFG_INTERRUPTS_ENABLED
philpem@0 67 interrupt_n,
philpem@0 68 `endif
philpem@0 69 // From user logic
philpem@0 70 `ifdef CFG_USER_ENABLED
philpem@0 71 user_result,
philpem@0 72 user_complete,
philpem@0 73 `endif
philpem@0 74 `ifdef CFG_IWB_ENABLED
philpem@0 75 // Instruction Wishbone master
philpem@0 76 I_DAT_I,
philpem@0 77 I_ACK_I,
philpem@0 78 I_ERR_I,
philpem@0 79 I_RTY_I,
philpem@0 80 `endif
philpem@0 81 // Data Wishbone master
philpem@0 82 D_DAT_I,
philpem@0 83 D_ACK_I,
philpem@0 84 D_ERR_I,
philpem@0 85 D_RTY_I,
philpem@0 86 // Debug Slave port WishboneInterface
philpem@0 87 DEBUG_ADR_I,
philpem@0 88 DEBUG_DAT_I,
philpem@0 89 DEBUG_SEL_I,
philpem@0 90 DEBUG_WE_I,
philpem@0 91 DEBUG_CTI_I,
philpem@0 92 DEBUG_BTE_I,
philpem@0 93 DEBUG_LOCK_I,
philpem@0 94 DEBUG_CYC_I,
philpem@0 95 DEBUG_STB_I,
philpem@0 96 // ----- Outputs -------
philpem@0 97 `ifdef CFG_USER_ENABLED
philpem@0 98 user_valid,
philpem@0 99 user_opcode,
philpem@0 100 user_operand_0,
philpem@0 101 user_operand_1,
philpem@0 102 `endif
philpem@0 103 `ifdef CFG_IWB_ENABLED
philpem@0 104 // Instruction Wishbone master
philpem@0 105 I_DAT_O,
philpem@0 106 I_ADR_O,
philpem@0 107 I_CYC_O,
philpem@0 108 I_SEL_O,
philpem@0 109 I_STB_O,
philpem@0 110 I_WE_O,
philpem@0 111 I_CTI_O,
philpem@0 112 I_LOCK_O,
philpem@0 113 I_BTE_O,
philpem@0 114 `endif
philpem@0 115 // Data Wishbone master
philpem@0 116 D_DAT_O,
philpem@0 117 D_ADR_O,
philpem@0 118 D_CYC_O,
philpem@0 119 D_SEL_O,
philpem@0 120 D_STB_O,
philpem@0 121 D_WE_O,
philpem@0 122 D_CTI_O,
philpem@0 123 D_LOCK_O,
philpem@0 124 D_BTE_O,
philpem@0 125 // Debug Slave port WishboneInterface
philpem@0 126 DEBUG_ACK_O,
philpem@0 127 DEBUG_ERR_O,
philpem@0 128 DEBUG_RTY_O,
philpem@0 129 DEBUG_DAT_O
philpem@0 130 );
philpem@0 131
philpem@0 132 /////////////////////////////////////////////////////
philpem@0 133 // Inputs
philpem@0 134 /////////////////////////////////////////////////////
philpem@0 135
philpem@0 136 input clk_i; // Clock
philpem@0 137 input rst_i; // Reset
philpem@0 138
philpem@26 139 `ifdef CFG_DEBUG_ENABLED
philpem@26 140 `ifdef CFG_ALTERNATE_EBA
philpem@26 141 input at_debug; // GPIO input that maps EBA to DEBA
philpem@26 142 `endif
philpem@26 143 `endif
philpem@26 144
philpem@0 145 `ifdef CFG_INTERRUPTS_ENABLED
philpem@0 146 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
philpem@0 147 `endif
philpem@0 148
philpem@0 149 `ifdef CFG_USER_ENABLED
philpem@0 150 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
philpem@0 151 input user_complete; // Indicates the user-defined instruction result is valid
philpem@0 152 `endif
philpem@0 153
philpem@0 154 `ifdef CFG_IWB_ENABLED
philpem@0 155 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
philpem@0 156 input I_ACK_I; // Instruction Wishbone interface acknowledgement
philpem@0 157 input I_ERR_I; // Instruction Wishbone interface error
philpem@0 158 input I_RTY_I; // Instruction Wishbone interface retry
philpem@0 159 `endif
philpem@0 160
philpem@0 161 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
philpem@0 162 input D_ACK_I; // Data Wishbone interface acknowledgement
philpem@0 163 input D_ERR_I; // Data Wishbone interface error
philpem@0 164 input D_RTY_I; // Data Wishbone interface retry
philpem@0 165
philpem@0 166 input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address
philpem@0 167 input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data
philpem@0 168 input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select
philpem@0 169 input DEBUG_WE_I; // Debug monitor Wishbone interface write enable
philpem@0 170 input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type
philpem@0 171 input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type
philpem@0 172 input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer
philpem@0 173 input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle
philpem@0 174 input DEBUG_STB_I; // Debug monitor Wishbone interface strobe
philpem@0 175
philpem@0 176 /////////////////////////////////////////////////////
philpem@0 177 // Outputs
philpem@0 178 /////////////////////////////////////////////////////
philpem@0 179
philpem@0 180 `ifdef CFG_USER_ENABLED
philpem@0 181 output user_valid; // Indicates that user_opcode and user_operand_* are valid
philpem@0 182 wire user_valid;
philpem@0 183 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
philpem@0 184 reg [`LM32_USER_OPCODE_RNG] user_opcode;
philpem@0 185 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
philpem@0 186 wire [`LM32_WORD_RNG] user_operand_0;
philpem@0 187 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
philpem@0 188 wire [`LM32_WORD_RNG] user_operand_1;
philpem@0 189 `endif
philpem@0 190
philpem@0 191 `ifdef CFG_IWB_ENABLED
philpem@0 192 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
philpem@0 193 wire [`LM32_WORD_RNG] I_DAT_O;
philpem@0 194 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
philpem@0 195 wire [`LM32_WORD_RNG] I_ADR_O;
philpem@0 196 output I_CYC_O; // Instruction Wishbone interface cycle
philpem@0 197 wire I_CYC_O;
philpem@0 198 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
philpem@0 199 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
philpem@0 200 output I_STB_O; // Instruction Wishbone interface strobe
philpem@0 201 wire I_STB_O;
philpem@0 202 output I_WE_O; // Instruction Wishbone interface write enable
philpem@0 203 wire I_WE_O;
philpem@0 204 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
philpem@0 205 wire [`LM32_CTYPE_RNG] I_CTI_O;
philpem@0 206 output I_LOCK_O; // Instruction Wishbone interface lock bus
philpem@0 207 wire I_LOCK_O;
philpem@0 208 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
philpem@0 209 wire [`LM32_BTYPE_RNG] I_BTE_O;
philpem@0 210 `endif
philpem@0 211
philpem@0 212 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
philpem@0 213 wire [`LM32_WORD_RNG] D_DAT_O;
philpem@0 214 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
philpem@0 215 wire [`LM32_WORD_RNG] D_ADR_O;
philpem@0 216 output D_CYC_O; // Data Wishbone interface cycle
philpem@0 217 wire D_CYC_O;
philpem@0 218 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
philpem@0 219 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
philpem@0 220 output D_STB_O; // Data Wishbone interface strobe
philpem@0 221 wire D_STB_O;
philpem@0 222 output D_WE_O; // Data Wishbone interface write enable
philpem@0 223 wire D_WE_O;
philpem@0 224 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
philpem@0 225 wire [`LM32_CTYPE_RNG] D_CTI_O;
philpem@0 226 output D_LOCK_O; // Date Wishbone interface lock bus
philpem@0 227 wire D_LOCK_O;
philpem@0 228 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
philpem@0 229 wire [`LM32_BTYPE_RNG] D_BTE_O;
philpem@0 230
philpem@0 231 output DEBUG_ACK_O; // Debug monitor Wishbone ack
philpem@0 232 wire DEBUG_ACK_O;
philpem@0 233 output DEBUG_ERR_O; // Debug monitor Wishbone error
philpem@0 234 wire DEBUG_ERR_O;
philpem@0 235 output DEBUG_RTY_O; // Debug monitor Wishbone retry
philpem@0 236 wire DEBUG_RTY_O;
philpem@0 237 output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data
philpem@0 238 wire [`LM32_WORD_RNG] DEBUG_DAT_O;
philpem@0 239
philpem@0 240 /////////////////////////////////////////////////////
philpem@0 241 // Internal nets and registers
philpem@0 242 /////////////////////////////////////////////////////
philpem@0 243
philpem@0 244 `ifdef CFG_JTAG_ENABLED
philpem@0 245 // Signals between JTAG interface and CPU
philpem@0 246 wire [`LM32_BYTE_RNG] jtag_reg_d;
philpem@0 247 wire [`LM32_BYTE_RNG] jtag_reg_q;
philpem@0 248 wire jtag_update;
philpem@0 249 wire [2:0] jtag_reg_addr_d;
philpem@0 250 wire [2:0] jtag_reg_addr_q;
philpem@0 251 wire jtck;
philpem@0 252 wire jrstn;
philpem@0 253 `endif
philpem@0 254
philpem@0 255 `ifdef CFG_TRACE_ENABLED
philpem@0 256 // PC trace signals
philpem@0 257 wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
philpem@0 258 wire trace_pc_valid; // Indicates that a new trace PC is valid
philpem@0 259 wire trace_exception; // Indicates an exception has occured
philpem@0 260 wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
philpem@0 261 wire trace_eret; // Indicates an eret instruction has been executed
philpem@0 262 `ifdef CFG_DEBUG_ENABLED
philpem@0 263 wire trace_bret; // Indicates a bret instruction has been executed
philpem@0 264 `endif
philpem@0 265 `endif
philpem@0 266
philpem@0 267 /////////////////////////////////////////////////////
philpem@0 268 // Functions
philpem@0 269 /////////////////////////////////////////////////////
philpem@0 270
philpem@0 271 `include "lm32_functions.v"
philpem@0 272 /////////////////////////////////////////////////////
philpem@0 273 // Instantiations
philpem@0 274 /////////////////////////////////////////////////////
philpem@0 275
philpem@0 276 // LM32 CPU
philpem@0 277 lm32_cpu cpu (
philpem@0 278 // ----- Inputs -------
philpem@0 279 .clk_i (clk_i),
philpem@0 280 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
philpem@0 281 .clk_n_i (clk_n),
philpem@0 282 `endif
philpem@0 283 .rst_i (rst_i),
philpem@26 284 `ifdef CFG_DEBUG_ENABLED
philpem@26 285 `ifdef CFG_ALTERNATE_EBA
philpem@26 286 .at_debug (at_debug),
philpem@26 287 `endif
philpem@26 288 `endif
philpem@0 289 // From external devices
philpem@0 290 `ifdef CFG_INTERRUPTS_ENABLED
philpem@0 291 .interrupt_n (interrupt_n),
philpem@0 292 `endif
philpem@0 293 // From user logic
philpem@0 294 `ifdef CFG_USER_ENABLED
philpem@0 295 .user_result (user_result),
philpem@0 296 .user_complete (user_complete),
philpem@0 297 `endif
philpem@0 298 `ifdef CFG_JTAG_ENABLED
philpem@0 299 // From JTAG
philpem@0 300 .jtag_clk (jtck),
philpem@0 301 .jtag_update (jtag_update),
philpem@0 302 .jtag_reg_q (jtag_reg_q),
philpem@0 303 .jtag_reg_addr_q (jtag_reg_addr_q),
philpem@0 304 `endif
philpem@0 305 `ifdef CFG_IWB_ENABLED
philpem@0 306 // Instruction Wishbone master
philpem@0 307 .I_DAT_I (I_DAT_I),
philpem@0 308 .I_ACK_I (I_ACK_I),
philpem@0 309 .I_ERR_I (I_ERR_I),
philpem@0 310 .I_RTY_I (I_RTY_I),
philpem@0 311 `endif
philpem@0 312 // Data Wishbone master
philpem@0 313 .D_DAT_I (D_DAT_I),
philpem@0 314 .D_ACK_I (D_ACK_I),
philpem@0 315 .D_ERR_I (D_ERR_I),
philpem@0 316 .D_RTY_I (D_RTY_I),
philpem@0 317 // ----- Outputs -------
philpem@0 318 `ifdef CFG_TRACE_ENABLED
philpem@0 319 .trace_pc (trace_pc),
philpem@0 320 .trace_pc_valid (trace_pc_valid),
philpem@0 321 .trace_exception (trace_exception),
philpem@0 322 .trace_eid (trace_eid),
philpem@0 323 .trace_eret (trace_eret),
philpem@0 324 `ifdef CFG_DEBUG_ENABLED
philpem@0 325 .trace_bret (trace_bret),
philpem@0 326 `endif
philpem@0 327 `endif
philpem@0 328 `ifdef CFG_JTAG_ENABLED
philpem@0 329 .jtag_reg_d (jtag_reg_d),
philpem@0 330 .jtag_reg_addr_d (jtag_reg_addr_d),
philpem@0 331 `endif
philpem@0 332 `ifdef CFG_USER_ENABLED
philpem@0 333 .user_valid (user_valid),
philpem@0 334 .user_opcode (user_opcode),
philpem@0 335 .user_operand_0 (user_operand_0),
philpem@0 336 .user_operand_1 (user_operand_1),
philpem@0 337 `endif
philpem@0 338 `ifdef CFG_IWB_ENABLED
philpem@0 339 // Instruction Wishbone master
philpem@0 340 .I_DAT_O (I_DAT_O),
philpem@0 341 .I_ADR_O (I_ADR_O),
philpem@0 342 .I_CYC_O (I_CYC_O),
philpem@0 343 .I_SEL_O (I_SEL_O),
philpem@0 344 .I_STB_O (I_STB_O),
philpem@0 345 .I_WE_O (I_WE_O),
philpem@0 346 .I_CTI_O (I_CTI_O),
philpem@0 347 .I_LOCK_O (I_LOCK_O),
philpem@0 348 .I_BTE_O (I_BTE_O),
philpem@0 349 `endif
philpem@0 350 // Data Wishbone master
philpem@0 351 .D_DAT_O (D_DAT_O),
philpem@0 352 .D_ADR_O (D_ADR_O),
philpem@0 353 .D_CYC_O (D_CYC_O),
philpem@0 354 .D_SEL_O (D_SEL_O),
philpem@0 355 .D_STB_O (D_STB_O),
philpem@0 356 .D_WE_O (D_WE_O),
philpem@0 357 .D_CTI_O (D_CTI_O),
philpem@0 358 .D_LOCK_O (D_LOCK_O),
philpem@0 359 .D_BTE_O (D_BTE_O)
philpem@0 360 );
philpem@0 361
philpem@0 362 wire TRACE_ACK_O;
philpem@0 363 wire [`LM32_WORD_RNG] TRACE_DAT_O;
philpem@0 364 `ifdef CFG_TRACE_ENABLED
philpem@0 365 lm32_trace trace_module (.clk_i (clk_i),
philpem@0 366 .rst_i (rst_i),
philpem@0 367 .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]),
philpem@0 368 .we_i (DEBUG_WE_I),
philpem@0 369 .sel_i (DEBUG_SEL_I),
philpem@0 370 .dat_i (DEBUG_DAT_I),
philpem@0 371 .adr_i (DEBUG_ADR_I),
philpem@0 372 .trace_pc (trace_pc),
philpem@0 373 .trace_eid (trace_eid),
philpem@0 374 .trace_eret (trace_eret),
philpem@0 375 .trace_bret (trace_bret),
philpem@0 376 .trace_pc_valid (trace_pc_valid),
philpem@0 377 .trace_exception (trace_exception),
philpem@0 378 .ack_o (TRACE_ACK_O),
philpem@0 379 .dat_o (TRACE_DAT_O));
philpem@0 380 `else
philpem@0 381 assign TRACE_ACK_O = 0;
philpem@0 382 assign TRACE_DAT_O = 0;
philpem@0 383 `endif
philpem@0 384 `ifdef DEBUG_ROM
philpem@0 385 wire ROM_ACK_O;
philpem@0 386 wire [`LM32_WORD_RNG] ROM_DAT_O;
philpem@0 387
philpem@0 388 assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
philpem@0 389 assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
philpem@0 390
philpem@0 391 // ROM monitor
philpem@0 392 lm32_monitor debug_rom (
philpem@0 393 // ----- Inputs -------
philpem@0 394 .clk_i (clk_i),
philpem@0 395 .rst_i (rst_i),
philpem@8 396 .MON_ADR_I (DEBUG_ADR_I[10:2]),
philpem@0 397 .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
philpem@0 398 .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
philpem@0 399 .MON_WE_I (DEBUG_WE_I),
philpem@0 400 .MON_SEL_I (DEBUG_SEL_I),
philpem@0 401 .MON_DAT_I (DEBUG_DAT_I),
philpem@0 402 // ----- Outputs ------
philpem@0 403 .MON_RTY_O (DEBUG_RTY_O),
philpem@0 404 .MON_ERR_O (DEBUG_ERR_O),
philpem@0 405 .MON_ACK_O (ROM_ACK_O),
philpem@0 406 .MON_DAT_O (ROM_DAT_O)
philpem@0 407 );
philpem@0 408 `endif
philpem@0 409
philpem@0 410 `ifdef CFG_JTAG_ENABLED
philpem@0 411 // JTAG cores
philpem@0 412 jtag_cores jtag_cores (
philpem@0 413 // ----- Inputs -----
philpem@0 414 `ifdef INCLUDE_LM32
philpem@0 415 .reg_d (jtag_reg_d),
philpem@0 416 .reg_addr_d (jtag_reg_addr_d),
philpem@0 417 `endif
philpem@0 418 // ----- Outputs -----
philpem@0 419 `ifdef INCLUDE_LM32
philpem@0 420 .reg_update (jtag_update),
philpem@0 421 .reg_q (jtag_reg_q),
philpem@0 422 .reg_addr_q (jtag_reg_addr_q),
philpem@0 423 `endif
philpem@0 424 .jtck (jtck),
philpem@0 425 .jrstn (jrstn)
philpem@0 426 );
philpem@0 427 `endif
philpem@0 428
philpem@0 429 endmodule