spiprog.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
philpem@26 4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
philpem@26 5 // ALL RIGHTS RESERVED
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philpem@26 9 //
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philpem@26 11 //
philpem@26 12 // Lattice Semiconductor grants permission to use this code
philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
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philpem@0 17 //
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philpem@26 19 // functionality of this code. It is the user's responsibility to
philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
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philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : SPIPROG.v
philpem@0 40 // This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
philpem@0 41 // core. There are only three ER2 registers, one control register and two
philpem@0 42 // data registers, in this IP core. The control register is a 8-bit wide
philpem@0 43 // register for selecting which data register will be accessed when the
philpem@0 44 // Control/Data# bit in ER1 register is low. Data register 0 is a readonly
philpem@0 45 // ID register. It is composed of three register fields -- an 8-bit
philpem@0 46 // "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
philpem@0 47 // Data register 1 is a variable length register for sending commands to or
philpem@0 48 // receiving readback data from the SPI Serial FLASH device.
philpem@0 49 // Dependencies : None
philpem@0 50 // Version : 6.1.17
philpem@0 51 // 1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
philpem@0 52 // 2. Same as TYPEA and TYPEB modules, use falling edge clock
philpem@0 53 // for all TCK Flip-Flops.
philpem@0 54 // 3. Added 7 delay Flip-Flops so that the DR1 readback data from
philpem@0 55 // SPI Serial FLASH is in the byte boundary.
philpem@0 56 // Version : 7.0SP2, 3.0
philpem@0 57 // : No Change
philpem@0 58 // Version : 3.1
philpem@0 59 // : No Change
philpem@0 60 // =============================================================================
philpem@0 61 //---------------------------------------------------------------------------
philpem@0 62 //
philpem@0 63 //Name : SPIPROG.v
philpem@0 64 //
philpem@0 65 //Description:
philpem@0 66 //
philpem@0 67 // This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
philpem@0 68 // core. There are only three ER2 registers, one control register and two
philpem@0 69 // data registers, in this IP core. The control register is a 8-bit wide
philpem@0 70 // register for selecting which data register will be accessed when the
philpem@0 71 // Control/Data# bit in ER1 register is low. Data register 0 is a readonly
philpem@0 72 // ID register. It is composed of three register fields -- an 8-bit
philpem@0 73 // "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
philpem@0 74 // Data register 1 is a variable length register for sending commands to or
philpem@0 75 // receiving readback data from the SPI Serial FLASH device.
philpem@0 76 //
philpem@0 77 //$Log: spiprog.vhd,v $
philpem@0 78 //Revision 1.2 2004-09-09 11:43:26-07 jhsin
philpem@0 79 //1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
philpem@0 80 //2. Same as TYPEA and TYPEB modules, use falling edge clock
philpem@0 81 // for all TCK Flip-Flops.
philpem@0 82 //
philpem@0 83 //Revision 1.1 2004-08-12 13:22:05-07 jhsin
philpem@0 84 //Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary.
philpem@0 85 //
philpem@0 86 //Revision 1.0 2004-08-03 18:35:56-07 jhsin
philpem@0 87 //Initial revision
philpem@0 88 //
philpem@0 89 //
philpem@0 90
philpem@0 91 module SPIPROG (input JTCK ,
philpem@0 92 input JTDI ,
philpem@0 93 output JTDO2 ,
philpem@0 94 input JSHIFT ,
philpem@0 95 input JUPDATE ,
philpem@0 96 input JRSTN ,
philpem@0 97 input JCE2 ,
philpem@0 98 input SPIPROG_ENABLE ,
philpem@0 99 input CONTROL_DATAN ,
philpem@0 100 output SPI_C ,
philpem@0 101 output SPI_D ,
philpem@0 102 output SPI_SN ,
philpem@0 103 input SPI_Q);
philpem@0 104
philpem@0 105 wire er2Cr_enable ;
philpem@0 106 wire er2Dr0_enable;
philpem@0 107 wire er2Dr1_enable;
philpem@0 108
philpem@0 109 wire tdo_er2Cr ;
philpem@0 110 wire tdo_er2Dr0;
philpem@0 111 wire tdo_er2Dr1;
philpem@0 112
philpem@0 113 wire [7:0] encodedDrSelBits ;
philpem@0 114 wire [8:0] er2CrTdiBit ;
philpem@0 115 wire [8:0] er2Dr0TdiBit ;
philpem@0 116
philpem@0 117 wire captureDrER2;
philpem@0 118 reg spi_s ;
philpem@0 119 reg [6:0] spi_q_dly;
philpem@0 120
philpem@0 121 wire [7:0] ip_functionality_id;
philpem@0 122
philpem@0 123 genvar i;
philpem@0 124
philpem@0 125 // ------ Control Register 0 ------
philpem@0 126
philpem@0 127 assign er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN;
philpem@0 128
philpem@0 129 assign tdo_er2Cr = er2CrTdiBit[0];
philpem@0 130
philpem@0 131 // CR_BIT0_BIT7
philpem@0 132 generate
philpem@0 133 for(i=0; i<=7; i=i+1)
philpem@0 134 begin:CR_BIT0_BIT7
philpem@0 135 TYPEA BIT_N (.CLK (JTCK),
philpem@0 136 .RESET_N (JRSTN),
philpem@0 137 .CLKEN (er2Cr_enable),
philpem@0 138 .TDI (er2CrTdiBit[i + 1]),
philpem@0 139 .TDO (er2CrTdiBit[i]),
philpem@0 140 .DATA_OUT (encodedDrSelBits[i]),
philpem@0 141 .DATA_IN (encodedDrSelBits[i]),
philpem@0 142 .CAPTURE_DR (captureDrER2),
philpem@0 143 .UPDATE_DR (JUPDATE));
philpem@0 144 end
philpem@0 145 endgenerate // CR_BIT0_BIT7
philpem@0 146
philpem@0 147 assign er2CrTdiBit[8] = JTDI;
philpem@0 148
philpem@0 149 // ------ Data Register 0 ------
philpem@0 150 assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0;
philpem@0 151
philpem@0 152 assign tdo_er2Dr0 = er2Dr0TdiBit[0];
philpem@0 153
philpem@0 154 assign ip_functionality_id = 8'b00000001; //-- SPI Serial FLASH Programmer (0x01)
philpem@0 155
philpem@0 156 // DR0_BIT0_BIT7
philpem@0 157 generate
philpem@0 158 for(i=0; i<=7; i=i+1)
philpem@0 159 begin:DR0_BIT0_BIT7
philpem@0 160 TYPEB BIT_N (.CLK (JTCK),
philpem@0 161 .RESET_N (JRSTN),
philpem@0 162 .CLKEN (er2Dr0_enable),
philpem@0 163 .TDI (er2Dr0TdiBit[i + 1]),
philpem@0 164 .TDO (er2Dr0TdiBit[i]),
philpem@0 165 .DATA_IN (ip_functionality_id[i]),
philpem@0 166 .CAPTURE_DR (captureDrER2));
philpem@0 167 end
philpem@0 168 endgenerate // DR0_BIT0_BIT7
philpem@0 169
philpem@0 170 assign er2Dr0TdiBit[8] = JTDI;
philpem@0 171
philpem@0 172 // ------ Data Register 1 ------
philpem@0 173
philpem@0 174 assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ? 1'b1 : 1'b0;
philpem@0 175
philpem@0 176 assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s);
philpem@0 177
philpem@0 178 assign SPI_D = JTDI & er2Dr1_enable;
philpem@0 179
philpem@0 180 // SPI_S_Proc
philpem@0 181 always @(negedge JTCK or negedge JRSTN)
philpem@0 182 begin
philpem@0 183 if (~JRSTN)
philpem@0 184 spi_s <= 1'b0;
philpem@0 185 else
philpem@0 186 if (JUPDATE)
philpem@0 187 spi_s <= 1'b0;
philpem@0 188 else
philpem@0 189 spi_s <= er2Dr1_enable;
philpem@0 190 end
philpem@0 191
philpem@0 192 assign SPI_SN = ~spi_s;
philpem@0 193
philpem@0 194 // SPI_Q_Proc
philpem@0 195 always @(negedge JTCK or negedge JRSTN)
philpem@0 196 begin
philpem@0 197 if (~JRSTN)
philpem@0 198 spi_q_dly <= 'b0;
philpem@0 199 else
philpem@0 200 if (er2Dr1_enable)
philpem@0 201 spi_q_dly <= {spi_q_dly[5:0],SPI_Q};
philpem@0 202 end
philpem@0 203
philpem@0 204 assign tdo_er2Dr1 = spi_q_dly[6];
philpem@0 205
philpem@0 206 // ------ JTDO2 MUX ------
philpem@0 207
philpem@0 208 assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr :
philpem@0 209 (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 :
philpem@0 210 (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0;
philpem@0 211
philpem@0 212 assign captureDrER2 = ~JSHIFT & JCE2;
philpem@0 213
philpem@0 214 endmodule