typea.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
philpem@26 4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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philpem@26 7 //
philpem@26 8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
philpem@26 9 //
philpem@26 10 // Permission:
philpem@26 11 //
philpem@26 12 // Lattice Semiconductor grants permission to use this code
philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
philpem@26 15 //
philpem@26 16 // Disclaimer:
philpem@0 17 //
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philpem@26 19 // functionality of this code. It is the user's responsibility to
philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
philpem@26 22 //
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philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : TYPEA.v
philpem@0 40 // Description:
philpem@0 41 // This is one of the two types of cells that are used to create ER1/ER2
philpem@0 42 // register bits.
philpem@0 43 // Dependencies : None
philpem@0 44 // Version : 6.1.17
philpem@0 45 // The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the
philpem@0 46 // dedicate logic JTAG_PORT didn't act as what their names implied.
philpem@0 47 // The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR.
philpem@0 48 // The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR.
philpem@0 49 // These had caused a lot of headaches for a long time and now they are
philpem@0 50 // fixed by:
philpem@0 51 // (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create
philpem@0 52 // CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers.
philpem@0 53 // (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals
philpem@0 54 // have the same waveform of ENABLE_ER2) directly to be the CLKEN
philpem@0 55 // of all typeA, typeB bits in the ER1, ER2 registers.
philpem@0 56 // (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable
philpem@0 57 // of the holding flip-flop.
philpem@0 58 // These changes caused ispTracy.vhd and cge.dat changes and the new
philpem@0 59 // CGE.exe version will be 1.3.5.
philpem@0 60 // Version : 7.0SP2, 3.0
philpem@0 61 // : No Change
philpem@0 62 // Version : 3.1
philpem@0 63 // : No Change
philpem@0 64 // =============================================================================
philpem@0 65 module TYPEA(
philpem@0 66 input CLK,
philpem@0 67 input RESET_N,
philpem@0 68 input CLKEN,
philpem@0 69 input TDI,
philpem@0 70 output TDO,
philpem@0 71 output reg DATA_OUT,
philpem@0 72 input DATA_IN,
philpem@0 73 input CAPTURE_DR,
philpem@0 74 input UPDATE_DR
philpem@0 75 );
philpem@0 76
philpem@0 77 reg tdoInt;
philpem@0 78
philpem@0 79
philpem@0 80 always @ (negedge CLK or negedge RESET_N)
philpem@0 81 begin
philpem@0 82 if (RESET_N == 1'b0)
philpem@27 83 tdoInt <= 1'b0;
philpem@0 84 else if (CLK == 1'b0)
philpem@0 85 if (CLKEN == 1'b1)
philpem@0 86 if (CAPTURE_DR == 1'b0)
philpem@27 87 tdoInt <= TDI;
philpem@0 88 else
philpem@27 89 tdoInt <= DATA_IN;
philpem@0 90 end
philpem@0 91
philpem@0 92 assign TDO = tdoInt;
philpem@0 93
philpem@0 94 always @ (negedge CLK or negedge RESET_N)
philpem@0 95 begin
philpem@0 96 if (RESET_N == 1'b0)
philpem@27 97 DATA_OUT <= 1'b0;
philpem@0 98 else if (CLK == 1'b0)
philpem@0 99 if (UPDATE_DR == 1'b1)
philpem@27 100 DATA_OUT <= tdoInt;
philpem@0 101 end
philpem@0 102 endmodule