typeb.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

philpem@26 1 // ==================================================================
philpem@26 2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
philpem@26 3 // ------------------------------------------------------------------
philpem@26 4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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philpem@26 8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
philpem@26 9 //
philpem@26 10 // Permission:
philpem@26 11 //
philpem@26 12 // Lattice Semiconductor grants permission to use this code
philpem@26 13 // pursuant to the terms of the Lattice Semiconductor Corporation
philpem@26 14 // Open Source License Agreement.
philpem@26 15 //
philpem@26 16 // Disclaimer:
philpem@0 17 //
philpem@26 18 // Lattice Semiconductor provides no warranty regarding the use or
philpem@26 19 // functionality of this code. It is the user's responsibility to
philpem@26 20 // verify the userís design for consistency and functionality through
philpem@26 21 // the use of formal verification methods.
philpem@26 22 //
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philpem@26 24 //
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philpem@26 36 // --------------------------------------------------------------------
philpem@0 37 // FILE DETAILS
philpem@0 38 // Project : LatticeMico32
philpem@0 39 // File : TYPEB.v
philpem@0 40 // Description:
philpem@0 41 // This is one of the two types of cells that are used to create ER1/ER2
philpem@0 42 // register bits.
philpem@0 43 // Dependencies : None
philpem@0 44 // Version : 6.1.17
philpem@0 45 // Modified typeb module to remove redundant DATA_OUT port.
philpem@0 46 // Version : 7.0SP2, 3.0
philpem@0 47 // : No Change
philpem@0 48 // Version : 3.1
philpem@0 49 // : No Change
philpem@0 50 // =============================================================================
philpem@0 51 module TYPEB
philpem@0 52 (
philpem@0 53 input CLK,
philpem@0 54 input RESET_N,
philpem@0 55 input CLKEN,
philpem@0 56 input TDI,
philpem@0 57 output TDO,
philpem@0 58 input DATA_IN,
philpem@0 59 input CAPTURE_DR
philpem@0 60 );
philpem@0 61
philpem@0 62 reg tdoInt;
philpem@0 63
philpem@0 64 always @ (negedge CLK or negedge RESET_N)
philpem@0 65 begin
philpem@0 66 if (RESET_N== 1'b0)
philpem@27 67 tdoInt <= 1'b0;
philpem@0 68 else if (CLK == 1'b0)
philpem@0 69 if (CLKEN==1'b1)
philpem@0 70 if (CAPTURE_DR==1'b0)
philpem@27 71 tdoInt <= TDI;
philpem@0 72 else
philpem@27 73 tdoInt <= DATA_IN;
philpem@0 74 end
philpem@0 75
philpem@0 76 assign TDO = tdoInt;
philpem@0 77
philpem@0 78 endmodule
philpem@0 79