document/lm32.htm

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     1.2 +++ b/document/lm32.htm	Fri Aug 13 01:13:04 2010 +0100
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     1.9 +<title>LatticeMico32 processor</title>
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   1.132 +</script>
   1.133 +<h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
   1.134 +
   1.135 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 
   1.136 + optimized for Lattice Semiconductor field-programmable gate arrays. </p>
   1.137 +
   1.138 +<p class="whs2"><span style="font-style: italic;"><I>*If the 
   1.139 + processor manual fails to open, see the note at the bottom of this page.</I></span></p>
   1.140 +
   1.141 +<h2>Revision History</h2>
   1.142 +
   1.143 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
   1.144 +<script language='JavaScript'><!--
   1.145 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>");
   1.146 +//--></script>
   1.147 +<col class="whs4">
   1.148 +<col class="whs5">
   1.149 +
   1.150 +<tr valign="top" class="whs6">
   1.151 +<td bgcolor="#DEE8F4" width="93px" class="whs7">
   1.152 +<p class=Table
   1.153 +	style="font-weight: bold;">Version</td>
   1.154 +<td bgcolor="#DEE8F4" width="598px" class="whs8">
   1.155 +<p class=Table
   1.156 +	style="font-weight: bold;">Description</td></tr>
   1.157 +
   1.158 +<tr valign="top" class="whs6">
   1.159 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   1.160 +<p class=Table
   1.161 +	style="font-weight: normal;">3.5</td>
   1.162 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   1.163 +<p class=whs10
   1.164 +	style="margin-left: 0px;">Support added to allow Inline Memories to 
   1.165 + be generated as non-power-of-two, as long as they are a multiple of 1024 
   1.166 + bytes</td></tr>
   1.167 +
   1.168 +<tr valign="top" class="whs6">
   1.169 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   1.170 +<p class=Table
   1.171 +	style="font-weight: normal;">3.3</td>
   1.172 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   1.173 +<p class=whs10
   1.174 +	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
   1.175 + connected through a local bus.</td></tr>
   1.176 +
   1.177 +<tr valign="top" class="whs6">
   1.178 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   1.179 +<p class=Table
   1.180 +	style="font-weight: normal;">3.2</td>
   1.181 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   1.182 +<p class=whs10
   1.183 +	style="margin-left: 0px;">Added Memory Type to instruction cache and 
   1.184 + data cache.</td></tr>
   1.185 +
   1.186 +<tr valign="top" class="whs6">
   1.187 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   1.188 +<p class=Table
   1.189 +	style="font-weight: normal;">3.1</td>
   1.190 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   1.191 +<p class="whs11">Added static predictor to improve the behavior 
   1.192 + of branches.</p>
   1.193 +<p class="whs11">Added support for optionally mapping the register 
   1.194 + file to EBRs (on-chip memory).</p>
   1.195 +<p class="whs11">Added support for selecting between distributed 
   1.196 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 
   1.197 + data caches.</td></tr>
   1.198 +
   1.199 +<tr valign="top" class="whs6">
   1.200 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   1.201 +<p class=Table
   1.202 +	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
   1.203 + </span></td>
   1.204 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   1.205 +<p class="whs11">Fixed incorrect handling of data cache miss 
   1.206 + in the presence of an instruction cache miss.</td></tr>
   1.207 +
   1.208 +<tr valign="top" class="whs6">
   1.209 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   1.210 +<p class="whs11">1.0</td>
   1.211 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   1.212 +<p class="whs11">Initial version.</td></tr>
   1.213 +<script language='JavaScript'><!--
   1.214 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>");
   1.215 +//--></script>
   1.216 +</table>
   1.217 +
   1.218 +&nbsp; 
   1.219 +
   1.220 +<h2>Dialog Box Parameters &#8211; 
   1.221 + General Tab</h2>
   1.222 +
   1.223 +<table x-use-null-cells cellspacing="0" class="whs12">
   1.224 +<col class="whs13">
   1.225 +<col class="whs14">
   1.226 +
   1.227 +<tr valign="top" class="whs15">
   1.228 +<td bgcolor="#DEE8F4" width="167px" class="whs16">
   1.229 +<p class=Table
   1.230 +	style="font-weight: bold;">Parameter</td>
   1.231 +<td bgcolor="#DEE8F4" width="524px" class="whs17">
   1.232 +<p class=Table
   1.233 +	style="font-weight: bold;">Description</td></tr>
   1.234 +
   1.235 +<tr valign="top" class="whs15">
   1.236 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.237 +<p class=Table
   1.238 +	style="font-weight: normal;">Instance Name</td>
   1.239 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.240 +<p class=Table
   1.241 +	style="margin-left: 14px;">Specifies the name of the LatticeMico32 
   1.242 + processor. Alphanumeric values and underscores are supported. The default 
   1.243 + is LM32.</td></tr>
   1.244 +
   1.245 +<tr valign="top" class="whs15">
   1.246 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   1.247 +<p class=Table
   1.248 +	style="font-weight: bold;">Settings</td>
   1.249 +</tr>
   1.250 +
   1.251 +<tr valign="top" class="whs15">
   1.252 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.253 +<p class=Table>Use EBRs for Register File</td>
   1.254 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.255 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr>
   1.256 +
   1.257 +<tr valign="top" class="whs15">
   1.258 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.259 +<p class=Table>Enable Divide</td>
   1.260 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.261 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 
   1.262 + modu</span>).</td></tr>
   1.263 +
   1.264 +<tr valign="top" class="whs15">
   1.265 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.266 +<p class=Table>Enable Sign Extend</td>
   1.267 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.268 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 
   1.269 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
   1.270 +
   1.271 +<tr valign="top" class="whs15">
   1.272 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.273 +<p class=Table>Location of Exception Handlers</td>
   1.274 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.275 +<p class=Table>Specifies the default value for the vector table. This can 
   1.276 + be changed by updating the EBA control register or status register.</p>
   1.277 +<p class=Table>This address must be aligned to a 256-byte boundary, since 
   1.278 + the hardware ignores the least-significant byte. Unpredictable behavior 
   1.279 + occurs when the exception base address and the exception vectors are not 
   1.280 + aligned on a 256-byte boundary.</td></tr>
   1.281 +
   1.282 +<tr valign="top" class="whs15">
   1.283 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   1.284 +<p class=Table
   1.285 +	style="font-weight: bold;">Multiplier Settings</td>
   1.286 +</tr>
   1.287 +
   1.288 +<tr valign="top" class="whs15">
   1.289 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.290 +<p class=Table>Enable Multiplier</td>
   1.291 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.292 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 
   1.293 + muli)</span>.</td></tr>
   1.294 +
   1.295 +<tr valign="top" class="whs15">
   1.296 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.297 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
   1.298 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.299 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
   1.300 +
   1.301 +<tr valign="top" class="whs15">
   1.302 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.303 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
   1.304 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.305 +<p class=Table>Enables the multiplier using LUTs.</td></tr>
   1.306 +
   1.307 +<tr valign="top" class="whs15">
   1.308 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   1.309 +<p class=Table
   1.310 +	style="font-weight: bold;">Instruction Cache</td>
   1.311 +</tr>
   1.312 +
   1.313 +<tr valign="top" class="whs15">
   1.314 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.315 +<p class=Table>Instruction Cache Enabled</td>
   1.316 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.317 +<p class=Table
   1.318 +	style="margin-left: 14px;">Determines whether an instruction cache 
   1.319 + is implemented.</td></tr>
   1.320 +
   1.321 +<tr valign="top" class="whs15">
   1.322 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.323 +<p class=Table>Number of Sets</td>
   1.324 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.325 +<p class=Table
   1.326 +	style="margin-left: 14px;">Specifies the number of sets in the instruction 
   1.327 + cache. Supported values are 128, 256, 512, 1024.</td></tr>
   1.328 +
   1.329 +<tr valign="top" class="whs15">
   1.330 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.331 +<p class=Table>Set Associativity</td>
   1.332 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.333 +<p class=Table
   1.334 +	style="margin-left: 14px;">Specifies the associativity of the instruction 
   1.335 + cache. Supported values are 1, 2.</td></tr>
   1.336 +
   1.337 +<tr valign="top" class="whs15">
   1.338 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.339 +<p class=Table>Bytes/Cache Line</td>
   1.340 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.341 +<p class=Table
   1.342 +	style="margin-left: 15px;">Specifies the number of bytes per instruction 
   1.343 + cache line. Supported values are 4, 8, 16.</td></tr>
   1.344 +
   1.345 +<tr valign="top" class="whs15">
   1.346 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.347 +<p class=Table>Memory Type</td>
   1.348 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.349 +<p class=Table
   1.350 +	style="margin-left: 15px;">Determines the FPGA resource to be used 
   1.351 + to implement the instruction cache. The decision can be left to the synthesis 
   1.352 + tool (Auto), or you can select from the following options:</p>
   1.353 +<ul type="disc" class="whs22">
   1.354 +	
   1.355 +	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   1.356 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
   1.357 +	
   1.358 +	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   1.359 + Implements the instruction cache as distributed RAM.</p></li>
   1.360 +	
   1.361 +	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   1.362 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
   1.363 +	
   1.364 +	<li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements 
   1.365 + the instruction cache as pseudo-dual-port EBR (one read port and one write 
   1.366 + port). </p></li>
   1.367 +</ul></td></tr>
   1.368 +
   1.369 +<tr valign="top" class="whs15">
   1.370 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   1.371 +<p class=Table
   1.372 +	style="font-weight: bold;">Debug Setting</td>
   1.373 +</tr>
   1.374 +
   1.375 +<tr valign="top" class="whs15">
   1.376 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.377 +<p class=Table>Enable Debug Interface</td>
   1.378 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.379 +<p class=Table>Includes the debugger stub in the CPU, which is required 
   1.380 + for debugging.</td></tr>
   1.381 +
   1.382 +<tr valign="top" class="whs15">
   1.383 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.384 +<p class=Table># of H/W Watchpoint Registers</td>
   1.385 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.386 +<p class=Table
   1.387 +	style="font-weight: normal;">Specifies the number of hardware watchpoint 
   1.388 + registers to be used in the debugging process.</td></tr>
   1.389 +
   1.390 +<tr valign="top" class="whs15">
   1.391 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.392 +<p class=Table>Enable Debugging Code in Flash or ROM</td>
   1.393 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.394 +<p class=Table
   1.395 +	style="font-weight: normal;">Enables you to set hardware breakpoints 
   1.396 + in read-only memory.</td></tr>
   1.397 +
   1.398 +<tr valign="top" class="whs15">
   1.399 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.400 +<p class=Table># of H/W Breakpoint Registers</td>
   1.401 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.402 +<p class=Table>Specifies the number of hardware breakpoint registers to 
   1.403 + be used in the debugging process.</td></tr>
   1.404 +
   1.405 +<tr valign="top" class="whs15">
   1.406 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.407 +<p class=Table>Enable PC Trace</td>
   1.408 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.409 +<p class=Table>Enables the Program Counter Trace feature, which enables 
   1.410 + you to run the program trace during debug to find items in your C or C++ 
   1.411 + Code during debug, such as breakpoints and exceptions. Refer to <span 
   1.412 + style="font-weight: bold;"><B>Help &gt; Help Contents &gt; Lattice Software 
   1.413 + Project Environment &gt; Concepts &gt; Program Counter Trace</B></span> for 
   1.414 + more information on Program Counter Trace.</td></tr>
   1.415 +
   1.416 +<tr valign="top" class="whs15">
   1.417 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.418 +<p class=Table>Trace Depth</td>
   1.419 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.420 +<p class=Table>Enables you to specify the depth of the Program Counter 
   1.421 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
   1.422 + Contents &gt; Lattice Software Project Environment &nbsp;&gt; 
   1.423 + Concepts &gt; Program Counter Trace</B></span> for more information on Program 
   1.424 + Counter Trace.</td></tr>
   1.425 +
   1.426 +<tr valign="top" class="whs15">
   1.427 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   1.428 +<p class=Table
   1.429 +	style="font-weight: bold;">Shifter Settings</td>
   1.430 +</tr>
   1.431 +
   1.432 +<tr valign="top" class="whs15">
   1.433 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.434 +<p class=Table>Enable Shifter</td>
   1.435 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.436 +<p>Enables the multi-bit shift instructions (sr, sri, sru, srui, sl, sli). 
   1.437 + </td></tr>
   1.438 +
   1.439 +<tr valign="top" class="whs15">
   1.440 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.441 +<p class=Table>Enable Piplined Barrel Shifter</td>
   1.442 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.443 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
   1.444 + to perform a shift operation in three cycles.</td></tr>
   1.445 +
   1.446 +<tr valign="top" class="whs15">
   1.447 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.448 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
   1.449 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.450 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 
   1.451 + shifter is implemented to shift one bit per cycle and take thirty-two 
   1.452 + cycles to complete.</td></tr>
   1.453 +
   1.454 +<tr valign="top" class="whs15">
   1.455 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   1.456 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
   1.457 +</tr>
   1.458 +
   1.459 +<tr valign="top" class="whs15">
   1.460 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.461 +<p class=Table>Data Cache Enabled</td>
   1.462 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.463 +<p class=Table>Determines whether a data cache is implemented.</td></tr>
   1.464 +
   1.465 +<tr valign="top" class="whs15">
   1.466 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.467 +<p class=Table>Number of Sets</td>
   1.468 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.469 +<p class=Table>Specifies the number of sets in the data cache. Supported 
   1.470 + values are 128, 256, 512, 1024.</td></tr>
   1.471 +
   1.472 +<tr valign="top" class="whs15">
   1.473 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.474 +<p class=Table>Set Associativity</td>
   1.475 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.476 +<p class=Table>Specifies the associativity of the data cache. Supported 
   1.477 + values are 1, 2.</td></tr>
   1.478 +
   1.479 +<tr valign="top" class="whs15">
   1.480 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.481 +<p class=Table>Bytes/Cache Line</td>
   1.482 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   1.483 +<p class=Table>Specifies the number of bytes per data cache line. Supported 
   1.484 + values are 4, 8, 16.</td></tr>
   1.485 +
   1.486 +<tr valign="top" class="whs15">
   1.487 +<td colspan="1" rowspan="1" width="167px" class="whs23">
   1.488 +<p class=Table>Memory Type</td>
   1.489 +<td colspan="1" rowspan="1" width="524px" class="whs24">
   1.490 +<p class=Table>Determines the FPGA resource to be used to implement the 
   1.491 + data cache. The decision can be left to the synthesis tool (Auto), or 
   1.492 + you can select from the following options:</p>
   1.493 +<ul>
   1.494 +	
   1.495 +	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   1.496 + Leaves the implementation of the data cache to the synthesis tool.</p></li>
   1.497 +	
   1.498 +	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   1.499 + Implements the data cache as distributed RAM.</p></li>
   1.500 +	
   1.501 +	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   1.502 + Implements the data cache as dual-port EBR (two read/write ports).</p></li>
   1.503 +</ul></td></tr>
   1.504 +</table>
   1.505 +
   1.506 +<p>&nbsp;</p>
   1.507 +
   1.508 +<h2>Dialog Box Parameters &#8211; 
   1.509 + Inline Memory Tab</h2>
   1.510 +
   1.511 +<table x-use-null-cells cellspacing="0" class="whs12">
   1.512 +<col class="whs13">
   1.513 +<col class="whs14">
   1.514 +
   1.515 +<tr valign="top" class="whs15">
   1.516 +<td bgcolor="#DEE8F4" width="167px" class="whs25">
   1.517 +<p class=Table
   1.518 +	style="font-weight: bold;">Parameter</td>
   1.519 +<td bgcolor="#DEE8F4" width="524px" class="whs26">
   1.520 +<p class=Table
   1.521 +	style="font-weight: bold;">Description</td></tr>
   1.522 +
   1.523 +<tr valign="top" class="whs15">
   1.524 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   1.525 +<p class=Table
   1.526 +	style="font-weight: bold;">Instruction Inline Memory</td>
   1.527 +</tr>
   1.528 +
   1.529 +<tr valign="top" class="whs15">
   1.530 +<td width="167px" class="whs28">
   1.531 +<p class=Table>Enable</td>
   1.532 +<td width="524px" class="whs29">
   1.533 +<p class=Table>Enables the instruction inline memory</td></tr>
   1.534 +
   1.535 +<tr valign="top" class="whs15">
   1.536 +<td width="167px" class="whs28">
   1.537 +<p class=Table>Instance Name</td>
   1.538 +<td width="524px" class="whs29">
   1.539 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 
   1.540 + values and underscores are supported. The default is Instruction_IM.</td></tr>
   1.541 +
   1.542 +<tr valign="top" class="whs15">
   1.543 +<td width="167px" class="whs28">
   1.544 +<p class=Table>Base Address</td>
   1.545 +<td width="524px" class="whs29">
   1.546 +<p class=Table>Specifies the base address for the instruction inline memory. 
   1.547 + The default is 0x10000000.</td></tr>
   1.548 +
   1.549 +<tr valign="top" class="whs15">
   1.550 +<td width="167px" class="whs28">
   1.551 +<p class=Table>Size of Memory in Bytes</td>
   1.552 +<td width="524px" class="whs29">
   1.553 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr>
   1.554 +
   1.555 +<tr valign="top" class="whs15">
   1.556 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   1.557 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
   1.558 +</tr>
   1.559 +
   1.560 +<tr valign="top" class="whs15">
   1.561 +<td width="167px" class="whs28">
   1.562 +<p class=Table>Initialization File Name</td>
   1.563 +<td width="524px" class="whs29">
   1.564 +<p class=Table>Specifies the name of the memory initialization file for 
   1.565 + instruction inline memory.</td></tr>
   1.566 +
   1.567 +<tr valign="top" class="whs15">
   1.568 +<td width="167px" class="whs28">
   1.569 +<p class=Table>File Format</td>
   1.570 +<td width="524px" class="whs29">
   1.571 +<p class=Table>Specifies the format of the memory initialization file: 
   1.572 + hex or binary.</td></tr>
   1.573 +
   1.574 +<tr valign="top" class="whs15">
   1.575 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   1.576 +<p class=Table
   1.577 +	style="font-weight: bold;">Data Inline Memory</td>
   1.578 +</tr>
   1.579 +
   1.580 +<tr valign="top" class="whs15">
   1.581 +<td width="167px" class="whs28">
   1.582 +<p class=Table>Enabled</td>
   1.583 +<td width="524px" class="whs29">
   1.584 +<p class=Table>Enables the data inline memory.</td></tr>
   1.585 +
   1.586 +<tr valign="top" class="whs15">
   1.587 +<td width="167px" class="whs28">
   1.588 +<p class=Table>Instance Name</td>
   1.589 +<td width="524px" class="whs29">
   1.590 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 
   1.591 + values and underscores are supported. The default is Data_IM.</td></tr>
   1.592 +
   1.593 +<tr valign="top" class="whs15">
   1.594 +<td width="167px" class="whs28">
   1.595 +<p class=Table>Base Address</td>
   1.596 +<td width="524px" class="whs29">
   1.597 +<p class=Table>Specifies the base address for the data inline memory. The 
   1.598 + default is 0x20000000.</td></tr>
   1.599 +
   1.600 +<tr valign="top" class="whs15">
   1.601 +<td width="167px" class="whs28">
   1.602 +<p class=Table>Size of Memory in Bytes</td>
   1.603 +<td width="524px" class="whs29">
   1.604 +<p class=Table>Specifies the size of the data inline memory.</td></tr>
   1.605 +
   1.606 +<tr valign="top" class="whs15">
   1.607 +<td colspan="2" rowspan="1" width="691px" class="whs27">
   1.608 +<p class=Table
   1.609 +	style="font-weight: bold;">Memory File</td>
   1.610 +</tr>
   1.611 +
   1.612 +<tr valign="top" class="whs15">
   1.613 +<td colspan="1" rowspan="1" width="167px" class="whs28">
   1.614 +<p class=Table>Initialization File Name</td>
   1.615 +<td colspan="1" rowspan="1" width="524px" class="whs29">
   1.616 +<p class=Table>Specifies the name of the memory initialization file for 
   1.617 + data inline memory.</td></tr>
   1.618 +
   1.619 +<tr valign="top" class="whs15">
   1.620 +<td colspan="1" rowspan="1" width="167px" class="whs30">
   1.621 +<p class=Table>File Format</td>
   1.622 +<td colspan="1" rowspan="1" width="524px" class="whs31">
   1.623 +<p class=Table>Specifies the format of the memory initialization file: 
   1.624 + hex or binary.</td></tr>
   1.625 +</table>
   1.626 +
   1.627 +<p>&nbsp;</p>
   1.628 +
   1.629 +<p>For the revision history of the component RTL files, refer to the header 
   1.630 + of each component Verilog source file. </p>
   1.631 +
   1.632 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 
   1.633 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 
   1.634 + and then click the note button.</p>
   1.635 +
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