1.1 --- a/lm32_monitor.v Sun Apr 04 20:40:03 2010 +0100 1.2 +++ b/lm32_monitor.v Fri Aug 13 01:13:04 2010 +0100 1.3 @@ -43,9 +43,6 @@ 1.4 MON_SEL_I, 1.5 MON_STB_I, 1.6 MON_WE_I, 1.7 - MON_LOCK_I, 1.8 - MON_CTI_I, 1.9 - MON_BTE_I, 1.10 // ----- Outputs ------- 1.11 MON_ACK_O, 1.12 MON_RTY_O, 1.13 @@ -59,15 +56,12 @@ 1.14 1.15 input clk_i; // Wishbone clock 1.16 input rst_i; // Wishbone reset 1.17 -input [`LM32_WORD_RNG] MON_ADR_I; // Wishbone address 1.18 +input [10:2] MON_ADR_I; // Wishbone address 1.19 input MON_STB_I; // Wishbone strobe 1.20 input MON_CYC_I; // Wishbone cycle 1.21 input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data 1.22 input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select 1.23 input MON_WE_I; // Wishbone write enable 1.24 -input MON_LOCK_I; // Wishbone locked transfer 1.25 -input [`LM32_CTYPE_RNG] MON_CTI_I; // Wishbone cycle type 1.26 -input [`LM32_BTYPE_RNG] MON_BTE_I; // Wishbone burst type 1.27 1.28 ///////////////////////////////////////////////////// 1.29 // Outputs