jtag_cores.v

changeset 14
54dd95f89113
parent 0
cd0b58aa6f83
child 15
27f96ec74b85
     1.1 --- a/jtag_cores.v	Sun Mar 06 19:23:51 2011 +0000
     1.2 +++ b/jtag_cores.v	Sun Mar 06 19:31:09 2011 +0000
     1.3 @@ -1,54 +1,6 @@
     1.4 -// ============================================================================
     1.5 -//                           COPYRIGHT NOTICE
     1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 -// ALL RIGHTS RESERVED
     1.8 -// This confidential and proprietary software may be used only as authorised by
     1.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 -// The entire notice above must be reproduced on all authorized copies and
    1.11 -// copies may only be made to the extent permitted by a licensing agreement from
    1.12 -// Lattice Semiconductor Corporation.
    1.13 -//
    1.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 -// U.S.A                                   email: techsupport@latticesemi.com
    1.18 -// ============================================================================/
    1.19 -//                         FILE DETAILS
    1.20 -// Project          : LatticeMico32
    1.21 -// File             : jtag_cores.v
    1.22 -// Title            : Instantiates all IP cores on JTAG chain.
    1.23 -// Dependencies     : system_conf.v
    1.24 -// Version          : 6.0.14
    1.25 -//                  : modified to use jtagconn for LM32,
    1.26 -//                  : all technologies 7/10/07
    1.27 -// Version          : 7.0SP2, 3.0
    1.28 -//                  : No Change
    1.29 -// Version          : 3.1
    1.30 -//                  : No Change
    1.31 -// ============================================================================
    1.32 +// TODO
    1.33  
    1.34 -`include "system_conf.v"
    1.35 -
    1.36 -/////////////////////////////////////////////////////
    1.37 -// jtagconn16 Module Definition
    1.38 -/////////////////////////////////////////////////////
    1.39 -
    1.40 -module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
    1.41 -    input  er2_tdo ; 
    1.42 -    output jtck ; 
    1.43 -    output jtdi ; 
    1.44 -    output jshift ; 
    1.45 -    output jupdate ; 
    1.46 -    output jrstn ; 
    1.47 -    output jce2 ; 
    1.48 -    output ip_enable ; 
    1.49 -endmodule
    1.50 -
    1.51 -/////////////////////////////////////////////////////
    1.52 -// Module interface
    1.53 -/////////////////////////////////////////////////////
    1.54 -
    1.55 -(* syn_hier="hard" *) module jtag_cores (
    1.56 +module jtag_cores (
    1.57      // ----- Inputs -------
    1.58      reg_d,
    1.59      reg_addr_d,
    1.60 @@ -58,19 +10,11 @@
    1.61      reg_addr_q,
    1.62      jtck,
    1.63      jrstn
    1.64 -    );
    1.65 -    
    1.66 -/////////////////////////////////////////////////////
    1.67 -// Inputs
    1.68 -/////////////////////////////////////////////////////
    1.69 +);
    1.70  
    1.71  input [7:0] reg_d;
    1.72  input [2:0] reg_addr_d;
    1.73  
    1.74 -/////////////////////////////////////////////////////
    1.75 -// Outputs
    1.76 -/////////////////////////////////////////////////////
    1.77 -   
    1.78  output reg_update;
    1.79  wire   reg_update;
    1.80  output [7:0] reg_q;
    1.81 @@ -79,47 +23,16 @@
    1.82  wire   [2:0] reg_addr_q;
    1.83  
    1.84  output jtck;
    1.85 -wire   jtck; 	/* synthesis syn_keep=1 */
    1.86 +wire   jtck;
    1.87  output jrstn;
    1.88 -wire   jrstn;  /* synthesis syn_keep=1 */	
    1.89 -
    1.90 -/////////////////////////////////////////////////////
    1.91 -// Instantiations
    1.92 -/////////////////////////////////////////////////////
    1.93 +wire   jrstn;
    1.94  
    1.95 -wire jtdi;          /* synthesis syn_keep=1 */
    1.96 -wire er2_tdo2;      /* synthesis syn_keep=1 */
    1.97 -wire jshift;        /* synthesis syn_keep=1 */
    1.98 -wire jupdate;       /* synthesis syn_keep=1 */
    1.99 -wire jce2;          /* synthesis syn_keep=1 */
   1.100 -wire ip_enable;     /* synthesis syn_keep=1 */
   1.101 -    
   1.102 -(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
   1.103 -    .er2_tdo        (er2_tdo2),
   1.104 -    .jtck           (jtck),
   1.105 -    .jtdi           (jtdi),
   1.106 -    .jshift         (jshift),
   1.107 -    .jupdate        (jupdate),
   1.108 -    .jrstn          (jrstn),
   1.109 -    .jce2           (jce2),
   1.110 -    .ip_enable      (ip_enable)
   1.111 -);
   1.112 -    
   1.113 -(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
   1.114 -    .JTCK           (jtck),
   1.115 -    .JTDI           (jtdi),
   1.116 -    .JTDO2          (er2_tdo2),
   1.117 -    .JSHIFT         (jshift),
   1.118 -    .JUPDATE        (jupdate),
   1.119 -    .JRSTN          (jrstn),
   1.120 -    .JCE2           (jce2),
   1.121 -    .JTAGREG_ENABLE (ip_enable),
   1.122 -    .CONTROL_DATAN  (),
   1.123 -    .REG_UPDATE     (reg_update),
   1.124 -    .REG_D          (reg_d),
   1.125 -    .REG_ADDR_D     (reg_addr_d),
   1.126 -    .REG_Q          (reg_q),
   1.127 -    .REG_ADDR_Q     (reg_addr_q)
   1.128 -    );
   1.129 +assign reg_d = 8'hxx;
   1.130 +assign reg_addr_d = 3'bxxx;
   1.131 +assign reg_update = 1'b0;
   1.132 +assign reg_q = 8'hxx;
   1.133 +assign reg_addr_q = 3'bxxx;
   1.134 +assign jtck = 1'b0;
   1.135 +assign jrstn = 1'b1;
   1.136      
   1.137  endmodule