lm32_top.v

changeset 14
54dd95f89113
parent 12
e8125a6a3bd8
child 16
5fb37de64edc
     1.1 --- a/lm32_top.v	Sun Mar 06 19:23:51 2011 +0000
     1.2 +++ b/lm32_top.v	Sun Mar 06 19:31:09 2011 +0000
     1.3 @@ -57,16 +57,6 @@
     1.4      D_ACK_I,
     1.5      D_ERR_I,
     1.6      D_RTY_I,
     1.7 -    // Debug Slave port WishboneInterface
     1.8 -    DEBUG_ADR_I,
     1.9 -    DEBUG_DAT_I,
    1.10 -    DEBUG_SEL_I,
    1.11 -    DEBUG_WE_I,
    1.12 -    DEBUG_CTI_I,
    1.13 -    DEBUG_BTE_I,
    1.14 -    DEBUG_LOCK_I,
    1.15 -    DEBUG_CYC_I,
    1.16 -    DEBUG_STB_I,
    1.17      // ----- Outputs -------
    1.18  `ifdef CFG_USER_ENABLED    
    1.19      user_valid,
    1.20 @@ -95,12 +85,7 @@
    1.21      D_WE_O,
    1.22      D_CTI_O,
    1.23      D_LOCK_O,
    1.24 -    D_BTE_O,
    1.25 -    // Debug Slave port WishboneInterface
    1.26 -    DEBUG_ACK_O,
    1.27 -    DEBUG_ERR_O,
    1.28 -    DEBUG_RTY_O,
    1.29 -    DEBUG_DAT_O
    1.30 +    D_BTE_O
    1.31      );
    1.32  
    1.33  /////////////////////////////////////////////////////
    1.34 @@ -131,16 +116,6 @@
    1.35  input D_ERR_I;                                  // Data Wishbone interface error
    1.36  input D_RTY_I;                                  // Data Wishbone interface retry
    1.37  
    1.38 -input [`LM32_WORD_RNG] DEBUG_ADR_I;             // Debug monitor Wishbone interface address
    1.39 -input [`LM32_WORD_RNG] DEBUG_DAT_I;             // Debug monitor Wishbone interface write data
    1.40 -input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I;      // Debug monitor Wishbone interface byte select
    1.41 -input DEBUG_WE_I;                               // Debug monitor Wishbone interface write enable
    1.42 -input [`LM32_CTYPE_RNG] DEBUG_CTI_I;            // Debug monitor Wishbone interface cycle type
    1.43 -input [`LM32_BTYPE_RNG] DEBUG_BTE_I;            // Debug monitor Wishbone interface burst type
    1.44 -input DEBUG_LOCK_I;                             // Debug monitor Wishbone interface locked transfer
    1.45 -input DEBUG_CYC_I;                              // Debug monitor Wishbone interface cycle
    1.46 -input DEBUG_STB_I;                              // Debug monitor Wishbone interface strobe
    1.47 -
    1.48  /////////////////////////////////////////////////////
    1.49  // Outputs
    1.50  /////////////////////////////////////////////////////
    1.51 @@ -195,15 +170,6 @@
    1.52  wire   D_LOCK_O;
    1.53  output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
    1.54  wire   [`LM32_BTYPE_RNG] D_BTE_O;
    1.55 -
    1.56 -output DEBUG_ACK_O;                             // Debug monitor Wishbone ack
    1.57 -wire   DEBUG_ACK_O;             
    1.58 -output DEBUG_ERR_O;                             // Debug monitor Wishbone error
    1.59 -wire   DEBUG_ERR_O;
    1.60 -output DEBUG_RTY_O;                             // Debug monitor Wishbone retry
    1.61 -wire   DEBUG_RTY_O;
    1.62 -output [`LM32_WORD_RNG] DEBUG_DAT_O;            // Debug monitor Wishbone read data
    1.63 -wire   [`LM32_WORD_RNG] DEBUG_DAT_O;
    1.64    
    1.65  /////////////////////////////////////////////////////
    1.66  // Internal nets and registers 
    1.67 @@ -220,6 +186,7 @@
    1.68  wire jrstn;
    1.69  `endif
    1.70  
    1.71 +// TODO: get the trace signals out
    1.72  `ifdef CFG_TRACE_ENABLED
    1.73  // PC trace signals
    1.74  wire [`LM32_PC_RNG] trace_pc;                   // PC to trace (address of next non-sequential instruction)