1.1 --- a/jtag_cores.v Sun Mar 06 19:32:57 2011 +0000 1.2 +++ b/jtag_cores.v Sun Mar 06 19:48:34 2011 +0000 1.3 @@ -1,36 +1,60 @@ 1.4 -// TODO 1.5 +module jtag_cores ( 1.6 + input [7:0] reg_d, 1.7 + input [2:0] reg_addr_d, 1.8 + output reg_update, 1.9 + output [7:0] reg_q, 1.10 + output [2:0] reg_addr_q, 1.11 + output jtck, 1.12 + output jrstn 1.13 +); 1.14 1.15 -module jtag_cores ( 1.16 - // ----- Inputs ------- 1.17 - reg_d, 1.18 - reg_addr_d, 1.19 - // ----- Outputs ------- 1.20 - reg_update, 1.21 - reg_q, 1.22 - reg_addr_q, 1.23 - jtck, 1.24 - jrstn 1.25 +wire sel; 1.26 +wire tck; 1.27 +wire tdi; 1.28 +wire tdo; 1.29 +wire shift; 1.30 +wire update; 1.31 +wire reset; 1.32 + 1.33 +jtag_tap jtag_tap ( 1.34 + .sel(sel), 1.35 + .tck(tck), 1.36 + .tdi(tdi), 1.37 + .tdo(tdo), 1.38 + .shift(shift), 1.39 + .update(update), 1.40 + .reset(reset) 1.41 ); 1.42 1.43 -input [7:0] reg_d; 1.44 -input [2:0] reg_addr_d; 1.45 +reg [10:0] jtag_shift; 1.46 +reg [10:0] jtag_latched; 1.47 1.48 -output reg_update; 1.49 -wire reg_update; 1.50 -output [7:0] reg_q; 1.51 -wire [7:0] reg_q; 1.52 -output [2:0] reg_addr_q; 1.53 -wire [2:0] reg_addr_q; 1.54 +always @(posedge tck or posedge reset) 1.55 +begin 1.56 + if(reset) 1.57 + jtag_shift <= 11'b0; 1.58 + else begin 1.59 + if(shift) 1.60 + jtag_shift <= {tdi, jtag_shift[10:1]}; 1.61 + else 1.62 + jtag_shift <= {reg_d, reg_addr_d}; 1.63 + end 1.64 +end 1.65 1.66 -output jtck; 1.67 -wire jtck; 1.68 -output jrstn; 1.69 -wire jrstn; 1.70 +assign tdo = jtag_shift[0]; 1.71 1.72 -assign reg_update = 1'b0; 1.73 -assign reg_q = 8'hxx; 1.74 -assign reg_addr_q = 3'bxxx; 1.75 -assign jtck = 1'b0; 1.76 -assign jrstn = 1'b1; 1.77 - 1.78 +always @(posedge reg_update or posedge reset) 1.79 +begin 1.80 + if(reset) 1.81 + jtag_latched <= 11'b0; 1.82 + else 1.83 + jtag_latched <= jtag_shift; 1.84 +end 1.85 + 1.86 +assign reg_update = update & sel; 1.87 +assign reg_q = jtag_latched[10:3]; 1.88 +assign reg_addr_q = jtag_latched[2:0]; 1.89 +assign jtck = tck; 1.90 +assign jrstn = ~reset; 1.91 + 1.92 endmodule