lm32_cpu.v

changeset 26
73de224304c1
parent 22
35dc7ba83714
child 27
d6c693415d59
     1.1 --- a/lm32_cpu.v	Sun Mar 06 21:14:43 2011 +0000
     1.2 +++ b/lm32_cpu.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 @@ -1,24 +1,50 @@
     1.4 -// =============================================================================
     1.5 -//                           COPYRIGHT NOTICE
     1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 -// ALL RIGHTS RESERVED
     1.8 -// This confidential and proprietary software may be used only as authorised by
     1.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 -// The entire notice above must be reproduced on all authorized copies and
    1.11 -// copies may only be made to the extent permitted by a licensing agreement from
    1.12 -// Lattice Semiconductor Corporation.
    1.13 +//   ==================================================================
    1.14 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    1.15 +//   ------------------------------------------------------------------
    1.16 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    1.17 +//   ALL RIGHTS RESERVED 
    1.18 +//   ------------------------------------------------------------------
    1.19 +//
    1.20 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    1.21 +//
    1.22 +//   Permission:
    1.23 +//
    1.24 +//      Lattice Semiconductor grants permission to use this code
    1.25 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    1.26 +//      Open Source License Agreement.  
    1.27 +//
    1.28 +//   Disclaimer:
    1.29  //
    1.30 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.31 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.32 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.33 -// U.S.A                                   email: techsupport@latticesemi.com
    1.34 -// =============================================================================/
    1.35 +//      Lattice Semiconductor provides no warranty regarding the use or
    1.36 +//      functionality of this code. It is the user's responsibility to
    1.37 +//      verify the userís design for consistency and functionality through
    1.38 +//      the use of formal verification methods.
    1.39 +//
    1.40 +//   --------------------------------------------------------------------
    1.41 +//
    1.42 +//                  Lattice Semiconductor Corporation
    1.43 +//                  5555 NE Moore Court
    1.44 +//                  Hillsboro, OR 97214
    1.45 +//                  U.S.A
    1.46 +//
    1.47 +//                  TEL: 1-800-Lattice (USA and Canada)
    1.48 +//                         503-286-8001 (other locations)
    1.49 +//
    1.50 +//                  web: http://www.latticesemi.com/
    1.51 +//                  email: techsupport@latticesemi.com
    1.52 +//
    1.53 +//   --------------------------------------------------------------------
    1.54  //                         FILE DETAILS
    1.55  // Project          : LatticeMico32
    1.56  // File             : lm32_cpu.v
    1.57  // Title            : Top-level of CPU.
    1.58  // Dependencies     : lm32_include.v
    1.59  //
    1.60 +// Version 3.8
    1.61 +// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO.
    1.62 +// 2. Bug: EA now reports instruction that caused the data abort, rather than
    1.63 +//    next instruction.
    1.64 +//
    1.65  // Version 3.4
    1.66  // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
    1.67  //    never serviced.
    1.68 @@ -75,6 +101,11 @@
    1.69      clk_n_i,
    1.70  `endif    
    1.71      rst_i,
    1.72 +`ifdef CFG_DEBUG_ENABLED
    1.73 + `ifdef CFG_ALTERNATE_EBA
    1.74 +    at_debug,
    1.75 + `endif
    1.76 +`endif
    1.77      // From external devices
    1.78  `ifdef CFG_INTERRUPTS_ENABLED
    1.79      interrupt_n,
    1.80 @@ -212,6 +243,12 @@
    1.81  `endif    
    1.82  input rst_i;                                    // Reset
    1.83  
    1.84 +`ifdef CFG_DEBUG_ENABLED
    1.85 + `ifdef CFG_ALTERNATE_EBA
    1.86 +   input at_debug;                              // GPIO input that maps EBA to DEBA
    1.87 + `endif
    1.88 +`endif
    1.89 +
    1.90  `ifdef CFG_INTERRUPTS_ENABLED
    1.91  input [`LM32_INTERRUPT_RNG] interrupt_n;        // Interrupt pins, active-low
    1.92  `endif
    1.93 @@ -751,6 +788,11 @@
    1.94      // ----- Inputs -------
    1.95      .clk_i                  (clk_i),
    1.96      .rst_i                  (rst_i),
    1.97 +`ifdef CFG_DEBUG_ENABLED
    1.98 + `ifdef CFG_ALTERNATE_EBA
    1.99 +    .at_debug               (at_debug),
   1.100 + `endif
   1.101 +`endif
   1.102      // From pipeline
   1.103      .stall_a                (stall_a),
   1.104      .stall_f                (stall_f),
   1.105 @@ -1256,15 +1298,15 @@
   1.106     always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.107       if (rst_i == `TRUE)
   1.108         begin
   1.109 -	  regfile_raw_0 <= 1'b0;
   1.110 -	  regfile_raw_1 <= 1'b0;
   1.111 -	  w_result_d <= 32'b0;
   1.112 +	  regfile_raw_0 <= #1 1'b0;
   1.113 +	  regfile_raw_1 <= #1 1'b0;
   1.114 +	  w_result_d <= #1 32'b0;
   1.115         end
   1.116       else
   1.117         begin
   1.118 -	  regfile_raw_0 <= regfile_raw_0_nxt;
   1.119 -	  regfile_raw_1 <= regfile_raw_1_nxt;
   1.120 -	  w_result_d <= w_result;
   1.121 +	  regfile_raw_0 <= #1 regfile_raw_0_nxt;
   1.122 +	  regfile_raw_1 <= #1 regfile_raw_1_nxt;
   1.123 +	  w_result_d <= #1 w_result;
   1.124         end
   1.125     
   1.126     /*----------------------------------------------------------------------
   1.127 @@ -2090,14 +2132,14 @@
   1.128  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.129  begin
   1.130      if (rst_i == `TRUE)
   1.131 -        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
   1.132 +        eba <= #1 eba_reset[`LM32_PC_WIDTH+2-1:8];
   1.133      else
   1.134      begin
   1.135          if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
   1.136 -            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
   1.137 +            eba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8];
   1.138  `ifdef CFG_HW_DEBUG_ENABLED
   1.139          if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
   1.140 -            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
   1.141 +            eba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
   1.142  `endif
   1.143      end
   1.144  end
   1.145 @@ -2107,14 +2149,14 @@
   1.146  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.147  begin
   1.148      if (rst_i == `TRUE)
   1.149 -        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
   1.150 +        deba <= #1 deba_reset[`LM32_PC_WIDTH+2-1:8];
   1.151      else
   1.152      begin
   1.153          if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
   1.154 -            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
   1.155 +            deba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8];
   1.156  `ifdef CFG_HW_DEBUG_ENABLED
   1.157          if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
   1.158 -            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
   1.159 +            deba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
   1.160  `endif
   1.161      end
   1.162  end
   1.163 @@ -2125,9 +2167,9 @@
   1.164  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.165  begin
   1.166      if (rst_i == `TRUE)
   1.167 -        cc <= {`LM32_WORD_WIDTH{1'b0}};
   1.168 +        cc <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.169      else
   1.170 -        cc <= cc + 1'b1;
   1.171 +        cc <= #1 cc + 1'b1;
   1.172  end
   1.173  `endif
   1.174  
   1.175 @@ -2136,15 +2178,15 @@
   1.176  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.177  begin
   1.178      if (rst_i == `TRUE)
   1.179 -        data_bus_error_seen <= `FALSE;
   1.180 +        data_bus_error_seen <= #1 `FALSE;
   1.181      else
   1.182      begin
   1.183          // Set flag when bus error is detected
   1.184          if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
   1.185 -            data_bus_error_seen <= `TRUE;
   1.186 +            data_bus_error_seen <= #1 `TRUE;
   1.187          // Clear flag when exception is taken
   1.188          if ((exception_m == `TRUE) && (kill_m == `FALSE))
   1.189 -            data_bus_error_seen <= `FALSE;
   1.190 +            data_bus_error_seen <= #1 `FALSE;
   1.191      end
   1.192  end
   1.193  `endif
   1.194 @@ -2195,48 +2237,48 @@
   1.195  begin
   1.196      if (rst_i == `TRUE)
   1.197      begin
   1.198 -        valid_f <= `FALSE;
   1.199 -        valid_d <= `FALSE;
   1.200 -        valid_x <= `FALSE;
   1.201 -        valid_m <= `FALSE;
   1.202 -        valid_w <= `FALSE;
   1.203 +        valid_f <= #1 `FALSE;
   1.204 +        valid_d <= #1 `FALSE;
   1.205 +        valid_x <= #1 `FALSE;
   1.206 +        valid_m <= #1 `FALSE;
   1.207 +        valid_w <= #1 `FALSE;
   1.208      end
   1.209      else
   1.210      begin    
   1.211          if ((kill_f == `TRUE) || (stall_a == `FALSE))
   1.212  `ifdef LM32_CACHE_ENABLED
   1.213 -            valid_f <= valid_a;    
   1.214 +            valid_f <= #1 valid_a;    
   1.215  `else
   1.216 -            valid_f <= `TRUE;
   1.217 +            valid_f <= #1 `TRUE;
   1.218  `endif            
   1.219          else if (stall_f == `FALSE)
   1.220 -            valid_f <= `FALSE;            
   1.221 +            valid_f <= #1 `FALSE;            
   1.222  
   1.223          if (kill_d == `TRUE)
   1.224 -            valid_d <= `FALSE;
   1.225 +            valid_d <= #1 `FALSE;
   1.226          else if (stall_f == `FALSE)
   1.227 -            valid_d <= valid_f & !kill_f;
   1.228 +            valid_d <= #1 valid_f & !kill_f;
   1.229          else if (stall_d == `FALSE)
   1.230 -            valid_d <= `FALSE;
   1.231 +            valid_d <= #1 `FALSE;
   1.232         
   1.233          if (stall_d == `FALSE)
   1.234 -            valid_x <= valid_d & !kill_d;
   1.235 +            valid_x <= #1 valid_d & !kill_d;
   1.236          else if (kill_x == `TRUE)
   1.237 -            valid_x <= `FALSE;
   1.238 +            valid_x <= #1 `FALSE;
   1.239          else if (stall_x == `FALSE)
   1.240 -            valid_x <= `FALSE;
   1.241 +            valid_x <= #1 `FALSE;
   1.242  
   1.243          if (kill_m == `TRUE)
   1.244 -            valid_m <= `FALSE;
   1.245 +            valid_m <= #1 `FALSE;
   1.246          else if (stall_x == `FALSE)
   1.247 -            valid_m <= valid_x & !kill_x;
   1.248 +            valid_m <= #1 valid_x & !kill_x;
   1.249          else if (stall_m == `FALSE)
   1.250 -            valid_m <= `FALSE;
   1.251 +            valid_m <= #1 `FALSE;
   1.252  
   1.253          if (stall_m == `FALSE)
   1.254 -            valid_w <= valid_m & !kill_m;
   1.255 +            valid_w <= #1 valid_m & !kill_m;
   1.256          else 
   1.257 -            valid_w <= `FALSE;        
   1.258 +            valid_w <= #1 `FALSE;        
   1.259      end
   1.260  end
   1.261  
   1.262 @@ -2246,113 +2288,113 @@
   1.263      if (rst_i == `TRUE)
   1.264      begin
   1.265  `ifdef CFG_USER_ENABLED
   1.266 -        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
   1.267 +        user_opcode <= #1 {`LM32_USER_OPCODE_WIDTH{1'b0}};       
   1.268  `endif        
   1.269 -        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.270 -        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.271 -        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.272 -        branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};        
   1.273 -        x_result_sel_csr_x <= `FALSE;
   1.274 +        operand_0_x <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.275 +        operand_1_x <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.276 +        store_operand_x <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.277 +        branch_target_x <= #1 {`LM32_WORD_WIDTH{1'b0}};        
   1.278 +        x_result_sel_csr_x <= #1 `FALSE;
   1.279  `ifdef LM32_MC_ARITHMETIC_ENABLED
   1.280 -        x_result_sel_mc_arith_x <= `FALSE;
   1.281 +        x_result_sel_mc_arith_x <= #1 `FALSE;
   1.282  `endif
   1.283  `ifdef LM32_NO_BARREL_SHIFT    
   1.284 -        x_result_sel_shift_x <= `FALSE;
   1.285 +        x_result_sel_shift_x <= #1 `FALSE;
   1.286  `endif
   1.287  `ifdef CFG_SIGN_EXTEND_ENABLED
   1.288 -        x_result_sel_sext_x <= `FALSE;
   1.289 +        x_result_sel_sext_x <= #1 `FALSE;
   1.290  `endif  
   1.291 -	x_result_sel_logic_x <= `FALSE;
   1.292 +	x_result_sel_logic_x <= #1 `FALSE;
   1.293  `ifdef CFG_USER_ENABLED
   1.294 -        x_result_sel_user_x <= `FALSE;
   1.295 +        x_result_sel_user_x <= #1 `FALSE;
   1.296  `endif
   1.297 -        x_result_sel_add_x <= `FALSE;
   1.298 -        m_result_sel_compare_x <= `FALSE;
   1.299 +        x_result_sel_add_x <= #1 `FALSE;
   1.300 +        m_result_sel_compare_x <= #1 `FALSE;
   1.301  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.302 -        m_result_sel_shift_x <= `FALSE;
   1.303 +        m_result_sel_shift_x <= #1 `FALSE;
   1.304  `endif    
   1.305 -        w_result_sel_load_x <= `FALSE;
   1.306 +        w_result_sel_load_x <= #1 `FALSE;
   1.307  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.308 -        w_result_sel_mul_x <= `FALSE;
   1.309 +        w_result_sel_mul_x <= #1 `FALSE;
   1.310  `endif
   1.311 -        x_bypass_enable_x <= `FALSE;
   1.312 -        m_bypass_enable_x <= `FALSE;
   1.313 -        write_enable_x <= `FALSE;
   1.314 -        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
   1.315 -        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
   1.316 -        load_x <= `FALSE;
   1.317 -        store_x <= `FALSE;
   1.318 -        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
   1.319 -        sign_extend_x <= `FALSE;
   1.320 -        adder_op_x <= `FALSE;
   1.321 -        adder_op_x_n <= `FALSE;
   1.322 -        logic_op_x <= 4'h0;
   1.323 +        x_bypass_enable_x <= #1 `FALSE;
   1.324 +        m_bypass_enable_x <= #1 `FALSE;
   1.325 +        write_enable_x <= #1 `FALSE;
   1.326 +        write_idx_x <= #1 {`LM32_REG_IDX_WIDTH{1'b0}};
   1.327 +        csr_x <= #1 {`LM32_CSR_WIDTH{1'b0}};
   1.328 +        load_x <= #1 `FALSE;
   1.329 +        store_x <= #1 `FALSE;
   1.330 +        size_x <= #1 {`LM32_SIZE_WIDTH{1'b0}};
   1.331 +        sign_extend_x <= #1 `FALSE;
   1.332 +        adder_op_x <= #1 `FALSE;
   1.333 +        adder_op_x_n <= #1 `FALSE;
   1.334 +        logic_op_x <= #1 4'h0;
   1.335  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.336 -        direction_x <= `FALSE;
   1.337 +        direction_x <= #1 `FALSE;
   1.338  `endif
   1.339  `ifdef CFG_ROTATE_ENABLED
   1.340 -        rotate_x <= `FALSE;
   1.341 +        rotate_x <= #1 `FALSE;
   1.342  
   1.343  `endif
   1.344 -        branch_x <= `FALSE;
   1.345 -        branch_predict_x <= `FALSE;
   1.346 -        branch_predict_taken_x <= `FALSE;
   1.347 -        condition_x <= `LM32_CONDITION_U1;
   1.348 +        branch_x <= #1 `FALSE;
   1.349 +        branch_predict_x <= #1 `FALSE;
   1.350 +        branch_predict_taken_x <= #1 `FALSE;
   1.351 +        condition_x <= #1 `LM32_CONDITION_U1;
   1.352  `ifdef CFG_DEBUG_ENABLED
   1.353 -        break_x <= `FALSE;
   1.354 +        break_x <= #1 `FALSE;
   1.355  `endif
   1.356 -        scall_x <= `FALSE;
   1.357 -        eret_x <= `FALSE;
   1.358 +        scall_x <= #1 `FALSE;
   1.359 +        eret_x <= #1 `FALSE;
   1.360  `ifdef CFG_DEBUG_ENABLED
   1.361 -        bret_x <= `FALSE;
   1.362 +        bret_x <= #1 `FALSE;
   1.363  `endif
   1.364  `ifdef CFG_BUS_ERRORS_ENABLED
   1.365 -        bus_error_x <= `FALSE;
   1.366 -        data_bus_error_exception_m <= `FALSE;
   1.367 +        bus_error_x <= #1 `FALSE;
   1.368 +        data_bus_error_exception_m <= #1 `FALSE;
   1.369  `endif
   1.370 -        csr_write_enable_x <= `FALSE;
   1.371 -        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.372 -        branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.373 -        m_result_sel_compare_m <= `FALSE;
   1.374 +        csr_write_enable_x <= #1 `FALSE;
   1.375 +        operand_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.376 +        branch_target_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.377 +        m_result_sel_compare_m <= #1 `FALSE;
   1.378  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.379 -        m_result_sel_shift_m <= `FALSE;
   1.380 +        m_result_sel_shift_m <= #1 `FALSE;
   1.381  `endif    
   1.382 -        w_result_sel_load_m <= `FALSE;
   1.383 +        w_result_sel_load_m <= #1 `FALSE;
   1.384  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.385 -        w_result_sel_mul_m <= `FALSE;
   1.386 +        w_result_sel_mul_m <= #1 `FALSE;
   1.387  `endif
   1.388 -        m_bypass_enable_m <= `FALSE;
   1.389 -        branch_m <= `FALSE;
   1.390 -        branch_predict_m <= `FALSE;
   1.391 -	branch_predict_taken_m <= `FALSE;
   1.392 -        exception_m <= `FALSE;
   1.393 -        load_m <= `FALSE;
   1.394 -        store_m <= `FALSE;
   1.395 -        write_enable_m <= `FALSE;            
   1.396 -        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
   1.397 -        condition_met_m <= `FALSE;
   1.398 +        m_bypass_enable_m <= #1 `FALSE;
   1.399 +        branch_m <= #1 `FALSE;
   1.400 +        branch_predict_m <= #1 `FALSE;
   1.401 +	branch_predict_taken_m <= #1 `FALSE;
   1.402 +        exception_m <= #1 `FALSE;
   1.403 +        load_m <= #1 `FALSE;
   1.404 +        store_m <= #1 `FALSE;
   1.405 +        write_enable_m <= #1 `FALSE;            
   1.406 +        write_idx_m <= #1 {`LM32_REG_IDX_WIDTH{1'b0}};
   1.407 +        condition_met_m <= #1 `FALSE;
   1.408  `ifdef CFG_DCACHE_ENABLED
   1.409 -        dflush_m <= `FALSE;
   1.410 +        dflush_m <= #1 `FALSE;
   1.411  `endif
   1.412  `ifdef CFG_DEBUG_ENABLED
   1.413 -        debug_exception_m <= `FALSE;
   1.414 -        non_debug_exception_m <= `FALSE;        
   1.415 +        debug_exception_m <= #1 `FALSE;
   1.416 +        non_debug_exception_m <= #1 `FALSE;        
   1.417  `endif
   1.418 -        operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
   1.419 -        w_result_sel_load_w <= `FALSE;
   1.420 +        operand_w <= #1 {`LM32_WORD_WIDTH{1'b0}};        
   1.421 +        w_result_sel_load_w <= #1 `FALSE;
   1.422  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.423 -        w_result_sel_mul_w <= `FALSE;
   1.424 +        w_result_sel_mul_w <= #1 `FALSE;
   1.425  `endif
   1.426 -        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
   1.427 -        write_enable_w <= `FALSE;
   1.428 +        write_idx_w <= #1 {`LM32_REG_IDX_WIDTH{1'b0}};        
   1.429 +        write_enable_w <= #1 `FALSE;
   1.430  `ifdef CFG_DEBUG_ENABLED
   1.431 -        debug_exception_w <= `FALSE;
   1.432 -        non_debug_exception_w <= `FALSE;        
   1.433 +        debug_exception_w <= #1 `FALSE;
   1.434 +        non_debug_exception_w <= #1 `FALSE;        
   1.435  `else
   1.436 -        exception_w <= `FALSE;
   1.437 +        exception_w <= #1 `FALSE;
   1.438  `endif
   1.439  `ifdef CFG_BUS_ERRORS_ENABLED
   1.440 -        memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
   1.441 +        memop_pc_w <= #1 {`LM32_PC_WIDTH{1'b0}};
   1.442  `endif
   1.443      end
   1.444      else
   1.445 @@ -2362,105 +2404,105 @@
   1.446          if (stall_x == `FALSE)
   1.447          begin
   1.448  `ifdef CFG_USER_ENABLED
   1.449 -            user_opcode <= user_opcode_d;       
   1.450 +            user_opcode <= #1 user_opcode_d;       
   1.451  `endif        
   1.452 -            operand_0_x <= d_result_0;
   1.453 -            operand_1_x <= d_result_1;
   1.454 -            store_operand_x <= bypass_data_1;
   1.455 -            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
   1.456 -            x_result_sel_csr_x <= x_result_sel_csr_d;
   1.457 +            operand_0_x <= #1 d_result_0;
   1.458 +            operand_1_x <= #1 d_result_1;
   1.459 +            store_operand_x <= #1 bypass_data_1;
   1.460 +            branch_target_x <= #1 branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
   1.461 +            x_result_sel_csr_x <= #1 x_result_sel_csr_d;
   1.462  `ifdef LM32_MC_ARITHMETIC_ENABLED
   1.463 -            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
   1.464 +            x_result_sel_mc_arith_x <= #1 x_result_sel_mc_arith_d;
   1.465  `endif
   1.466  `ifdef LM32_NO_BARREL_SHIFT    
   1.467 -            x_result_sel_shift_x <= x_result_sel_shift_d;
   1.468 +            x_result_sel_shift_x <= #1 x_result_sel_shift_d;
   1.469  `endif
   1.470  `ifdef CFG_SIGN_EXTEND_ENABLED
   1.471 -            x_result_sel_sext_x <= x_result_sel_sext_d;
   1.472 +            x_result_sel_sext_x <= #1 x_result_sel_sext_d;
   1.473  `endif    
   1.474 -	    x_result_sel_logic_x <= x_result_sel_logic_d;
   1.475 +	    x_result_sel_logic_x <= #1 x_result_sel_logic_d;
   1.476  `ifdef CFG_USER_ENABLED
   1.477 -            x_result_sel_user_x <= x_result_sel_user_d;
   1.478 +            x_result_sel_user_x <= #1 x_result_sel_user_d;
   1.479  `endif
   1.480 -            x_result_sel_add_x <= x_result_sel_add_d;
   1.481 -            m_result_sel_compare_x <= m_result_sel_compare_d;
   1.482 +            x_result_sel_add_x <= #1 x_result_sel_add_d;
   1.483 +            m_result_sel_compare_x <= #1 m_result_sel_compare_d;
   1.484  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.485 -            m_result_sel_shift_x <= m_result_sel_shift_d;
   1.486 +            m_result_sel_shift_x <= #1 m_result_sel_shift_d;
   1.487  `endif    
   1.488 -            w_result_sel_load_x <= w_result_sel_load_d;
   1.489 +            w_result_sel_load_x <= #1 w_result_sel_load_d;
   1.490  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.491 -            w_result_sel_mul_x <= w_result_sel_mul_d;
   1.492 +            w_result_sel_mul_x <= #1 w_result_sel_mul_d;
   1.493  `endif
   1.494 -            x_bypass_enable_x <= x_bypass_enable_d;
   1.495 -            m_bypass_enable_x <= m_bypass_enable_d;
   1.496 -            load_x <= load_d;
   1.497 -            store_x <= store_d;
   1.498 -            branch_x <= branch_d;
   1.499 -	    branch_predict_x <= branch_predict_d;
   1.500 -	    branch_predict_taken_x <= branch_predict_taken_d;
   1.501 -	    write_idx_x <= write_idx_d;
   1.502 -            csr_x <= csr_d;
   1.503 -            size_x <= size_d;
   1.504 -            sign_extend_x <= sign_extend_d;
   1.505 -            adder_op_x <= adder_op_d;
   1.506 -            adder_op_x_n <= ~adder_op_d;
   1.507 -            logic_op_x <= logic_op_d;
   1.508 +            x_bypass_enable_x <= #1 x_bypass_enable_d;
   1.509 +            m_bypass_enable_x <= #1 m_bypass_enable_d;
   1.510 +            load_x <= #1 load_d;
   1.511 +            store_x <= #1 store_d;
   1.512 +            branch_x <= #1 branch_d;
   1.513 +	    branch_predict_x <= #1 branch_predict_d;
   1.514 +	    branch_predict_taken_x <= #1 branch_predict_taken_d;
   1.515 +	    write_idx_x <= #1 write_idx_d;
   1.516 +            csr_x <= #1 csr_d;
   1.517 +            size_x <= #1 size_d;
   1.518 +            sign_extend_x <= #1 sign_extend_d;
   1.519 +            adder_op_x <= #1 adder_op_d;
   1.520 +            adder_op_x_n <= #1 ~adder_op_d;
   1.521 +            logic_op_x <= #1 logic_op_d;
   1.522  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.523 -            direction_x <= direction_d;
   1.524 +            direction_x <= #1 direction_d;
   1.525  `endif
   1.526  `ifdef CFG_ROTATE_ENABLED
   1.527 -            rotate_x <= rotate_d;
   1.528 +            rotate_x <= #1 rotate_d;
   1.529  `endif
   1.530 -            condition_x <= condition_d;
   1.531 -            csr_write_enable_x <= csr_write_enable_d;
   1.532 +            condition_x <= #1 condition_d;
   1.533 +            csr_write_enable_x <= #1 csr_write_enable_d;
   1.534  `ifdef CFG_DEBUG_ENABLED
   1.535 -            break_x <= break_d;
   1.536 +            break_x <= #1 break_d;
   1.537  `endif
   1.538 -            scall_x <= scall_d;
   1.539 +            scall_x <= #1 scall_d;
   1.540  `ifdef CFG_BUS_ERRORS_ENABLED
   1.541 -            bus_error_x <= bus_error_d;
   1.542 +            bus_error_x <= #1 bus_error_d;
   1.543  `endif
   1.544 -            eret_x <= eret_d;
   1.545 +            eret_x <= #1 eret_d;
   1.546  `ifdef CFG_DEBUG_ENABLED
   1.547 -            bret_x <= bret_d; 
   1.548 +            bret_x <= #1 bret_d; 
   1.549  `endif
   1.550 -            write_enable_x <= write_enable_d;
   1.551 +            write_enable_x <= #1 write_enable_d;
   1.552          end
   1.553          
   1.554          // X/M stage registers
   1.555  
   1.556          if (stall_m == `FALSE)
   1.557          begin
   1.558 -            operand_m <= x_result;
   1.559 -            m_result_sel_compare_m <= m_result_sel_compare_x;
   1.560 +            operand_m <= #1 x_result;
   1.561 +            m_result_sel_compare_m <= #1 m_result_sel_compare_x;
   1.562  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.563 -            m_result_sel_shift_m <= m_result_sel_shift_x;
   1.564 +            m_result_sel_shift_m <= #1 m_result_sel_shift_x;
   1.565  `endif    
   1.566              if (exception_x == `TRUE)
   1.567              begin
   1.568 -                w_result_sel_load_m <= `FALSE;
   1.569 +                w_result_sel_load_m <= #1 `FALSE;
   1.570  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.571 -                w_result_sel_mul_m <= `FALSE;
   1.572 +                w_result_sel_mul_m <= #1 `FALSE;
   1.573  `endif
   1.574              end
   1.575              else
   1.576              begin
   1.577 -                w_result_sel_load_m <= w_result_sel_load_x;
   1.578 +                w_result_sel_load_m <= #1 w_result_sel_load_x;
   1.579  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.580 -                w_result_sel_mul_m <= w_result_sel_mul_x;
   1.581 +                w_result_sel_mul_m <= #1 w_result_sel_mul_x;
   1.582  `endif
   1.583              end
   1.584 -            m_bypass_enable_m <= m_bypass_enable_x;
   1.585 +            m_bypass_enable_m <= #1 m_bypass_enable_x;
   1.586  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.587  `endif
   1.588 -            load_m <= load_x;
   1.589 -            store_m <= store_x;
   1.590 +            load_m <= #1 load_x;
   1.591 +            store_m <= #1 store_x;
   1.592  `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   1.593 -            branch_m <= branch_x && !branch_taken_x;
   1.594 +            branch_m <= #1 branch_x && !branch_taken_x;
   1.595  `else
   1.596 -            branch_m <= branch_x;
   1.597 -	    branch_predict_m <= branch_predict_x;
   1.598 -	    branch_predict_taken_m <= branch_predict_taken_x;
   1.599 +            branch_m <= #1 branch_x;
   1.600 +	    branch_predict_m <= #1 branch_predict_x;
   1.601 +	    branch_predict_taken_m <= #1 branch_predict_taken_x;
   1.602  `endif
   1.603  `ifdef CFG_DEBUG_ENABLED
   1.604  	   // Data bus errors are generated by the wishbone and are
   1.605 @@ -2469,45 +2511,48 @@
   1.606  	   // in same cycle (causing a debug exception). Handle non
   1.607  	   // -debug exception first!
   1.608              if (non_debug_exception_x == `TRUE) 
   1.609 -                write_idx_m <= `LM32_EA_REG;
   1.610 +                write_idx_m <= #1 `LM32_EA_REG;
   1.611              else if (debug_exception_x == `TRUE)
   1.612 -                write_idx_m <= `LM32_BA_REG;
   1.613 +                write_idx_m <= #1 `LM32_BA_REG;
   1.614              else 
   1.615 -                write_idx_m <= write_idx_x;
   1.616 +                write_idx_m <= #1 write_idx_x;
   1.617  `else
   1.618              if (exception_x == `TRUE)
   1.619 -                write_idx_m <= `LM32_EA_REG;
   1.620 +                write_idx_m <= #1 `LM32_EA_REG;
   1.621              else 
   1.622 -                write_idx_m <= write_idx_x;
   1.623 +                write_idx_m <= #1 write_idx_x;
   1.624  `endif
   1.625 -            condition_met_m <= condition_met_x;
   1.626 +            condition_met_m <= #1 condition_met_x;
   1.627  `ifdef CFG_DEBUG_ENABLED
   1.628  	   if (exception_x == `TRUE)
   1.629  	     if ((dc_re == `TRUE)
   1.630 + `ifdef CFG_ALTERNATE_EBA
   1.631 +		 || (at_debug == `TRUE)
   1.632 + `endif
   1.633  		 || ((debug_exception_x == `TRUE) 
   1.634  		     && (non_debug_exception_x == `FALSE)))
   1.635 -	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
   1.636 +	       branch_target_m <= #1 {deba, eid_x, {3{1'b0}}};
   1.637  	     else
   1.638 -	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
   1.639 +	       branch_target_m <= #1 {eba, eid_x, {3{1'b0}}};
   1.640  	   else
   1.641 -	     branch_target_m <= branch_target_x;
   1.642 +	     branch_target_m <= #1 branch_target_x;
   1.643  `else
   1.644 -            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
   1.645 +            branch_target_m <= #1 exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
   1.646  `endif
   1.647  `ifdef CFG_TRACE_ENABLED
   1.648 -            eid_m <= eid_x;
   1.649 +            eid_m <= #1 eid_x;
   1.650  `endif
   1.651  `ifdef CFG_DCACHE_ENABLED
   1.652 -            dflush_m <= dflush_x;
   1.653 +            dflush_m <= #1 dflush_x;
   1.654  `endif
   1.655 -            eret_m <= eret_q_x;
   1.656 +            eret_m <= #1 eret_q_x;
   1.657  `ifdef CFG_DEBUG_ENABLED
   1.658 -            bret_m <= bret_q_x; 
   1.659 +            bret_m <= #1 bret_q_x; 
   1.660  `endif
   1.661 -            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
   1.662 +            write_enable_m <= #1 exception_x == `TRUE ? `TRUE : write_enable_x;            
   1.663  `ifdef CFG_DEBUG_ENABLED
   1.664 -            debug_exception_m <= debug_exception_x;
   1.665 -            non_debug_exception_m <= non_debug_exception_x;        
   1.666 +            debug_exception_m <= #1 debug_exception_x;
   1.667 +            non_debug_exception_m <= #1 non_debug_exception_x;        
   1.668  `endif
   1.669          end
   1.670          
   1.671 @@ -2515,11 +2560,11 @@
   1.672          if (stall_m == `FALSE)
   1.673          begin
   1.674              if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
   1.675 -                exception_m <= `TRUE;
   1.676 +                exception_m <= #1 `TRUE;
   1.677              else 
   1.678 -                exception_m <= `FALSE;
   1.679 +                exception_m <= #1 `FALSE;
   1.680  `ifdef CFG_BUS_ERRORS_ENABLED
   1.681 -	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
   1.682 +	   data_bus_error_exception_m <= #1    (data_bus_error_exception == `TRUE) 
   1.683  `ifdef CFG_DEBUG_ENABLED
   1.684  					 && (reset_exception == `FALSE)
   1.685  `endif
   1.686 @@ -2529,36 +2574,37 @@
   1.687                  
   1.688          // M/W stage registers
   1.689  `ifdef CFG_BUS_ERRORS_ENABLED
   1.690 -        operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
   1.691 +        operand_w <= #1 exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
   1.692  `else
   1.693 -        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
   1.694 +        operand_w <= #1 exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
   1.695  `endif
   1.696 -        w_result_sel_load_w <= w_result_sel_load_m;
   1.697 +        w_result_sel_load_w <= #1 w_result_sel_load_m;
   1.698  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.699 -        w_result_sel_mul_w <= w_result_sel_mul_m;
   1.700 +        w_result_sel_mul_w <= #1 w_result_sel_mul_m;
   1.701  `endif
   1.702 -        write_idx_w <= write_idx_m;
   1.703 +        write_idx_w <= #1 write_idx_m;
   1.704  `ifdef CFG_TRACE_ENABLED
   1.705 -        eid_w <= eid_m;
   1.706 -        eret_w <= eret_m;
   1.707 +        eid_w <= #1 eid_m;
   1.708 +        eret_w <= #1 eret_m;
   1.709  `ifdef CFG_DEBUG_ENABLED
   1.710 -        bret_w <= bret_m; 
   1.711 +        bret_w <= #1 bret_m; 
   1.712  `endif
   1.713  `endif
   1.714 -        write_enable_w <= write_enable_m;
   1.715 +        write_enable_w <= #1 write_enable_m;
   1.716  `ifdef CFG_DEBUG_ENABLED
   1.717 -        debug_exception_w <= debug_exception_m;
   1.718 -        non_debug_exception_w <= non_debug_exception_m;
   1.719 +        debug_exception_w <= #1 debug_exception_m;
   1.720 +        non_debug_exception_w <= #1 non_debug_exception_m;
   1.721  `else
   1.722 -        exception_w <= exception_m;
   1.723 +        exception_w <= #1 exception_m;
   1.724  `endif
   1.725  `ifdef CFG_BUS_ERRORS_ENABLED
   1.726          if (   (stall_m == `FALSE)
   1.727 +	    && (data_bus_error_exception == `FALSE)
   1.728              && (   (load_q_m == `TRUE) 
   1.729                  || (store_q_m == `TRUE)
   1.730                 )
   1.731  	   )
   1.732 -          memop_pc_w <= pc_m;
   1.733 +          memop_pc_w <= #1 pc_m;
   1.734  `endif
   1.735      end
   1.736  end
   1.737 @@ -2570,26 +2616,26 @@
   1.738  begin
   1.739      if (rst_i == `TRUE)
   1.740      begin
   1.741 -        use_buf <= `FALSE;
   1.742 -        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
   1.743 -        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
   1.744 +        use_buf <= #1 `FALSE;
   1.745 +        reg_data_buf_0 <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.746 +        reg_data_buf_1 <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.747      end
   1.748      else
   1.749      begin
   1.750          if (stall_d == `FALSE)
   1.751 -            use_buf <= `FALSE;
   1.752 +            use_buf <= #1 `FALSE;
   1.753          else if (use_buf == `FALSE)
   1.754          begin        
   1.755 -            reg_data_buf_0 <= reg_data_live_0;
   1.756 -            reg_data_buf_1 <= reg_data_live_1;
   1.757 -            use_buf <= `TRUE;
   1.758 +            reg_data_buf_0 <= #1 reg_data_live_0;
   1.759 +            reg_data_buf_1 <= #1 reg_data_live_1;
   1.760 +            use_buf <= #1 `TRUE;
   1.761          end        
   1.762          if (reg_write_enable_q_w == `TRUE)
   1.763          begin
   1.764              if (write_idx_w == read_idx_0_d)
   1.765 -                reg_data_buf_0 <= w_result;
   1.766 +                reg_data_buf_0 <= #1 w_result;
   1.767              if (write_idx_w == read_idx_1_d)
   1.768 -                reg_data_buf_1 <= w_result;
   1.769 +                reg_data_buf_1 <= #1 w_result;
   1.770          end
   1.771      end
   1.772  end
   1.773 @@ -2601,42 +2647,42 @@
   1.774  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.775  begin
   1.776      if (rst_i == `TRUE) begin
   1.777 -        registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
   1.778 -        registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
   1.779 -        registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
   1.780 -        registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
   1.781 -        registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
   1.782 -        registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
   1.783 -        registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
   1.784 -        registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
   1.785 -        registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
   1.786 -        registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
   1.787 -        registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
   1.788 -        registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
   1.789 -        registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
   1.790 -        registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
   1.791 -        registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
   1.792 -        registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
   1.793 -        registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
   1.794 -        registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
   1.795 -        registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
   1.796 -        registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
   1.797 -        registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
   1.798 -        registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
   1.799 -        registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
   1.800 -        registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
   1.801 -        registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
   1.802 -        registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
   1.803 -        registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
   1.804 -        registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
   1.805 -        registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
   1.806 -        registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
   1.807 -        registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
   1.808 -        registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
   1.809 +        registers[0] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.810 +        registers[1] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.811 +        registers[2] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.812 +        registers[3] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.813 +        registers[4] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.814 +        registers[5] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.815 +        registers[6] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.816 +        registers[7] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.817 +        registers[8] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.818 +        registers[9] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.819 +        registers[10] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.820 +        registers[11] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.821 +        registers[12] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.822 +        registers[13] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.823 +        registers[14] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.824 +        registers[15] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.825 +        registers[16] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.826 +        registers[17] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.827 +        registers[18] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.828 +        registers[19] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.829 +        registers[20] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.830 +        registers[21] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.831 +        registers[22] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.832 +        registers[23] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.833 +        registers[24] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.834 +        registers[25] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.835 +        registers[26] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.836 +        registers[27] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.837 +        registers[28] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.838 +        registers[29] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.839 +        registers[30] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.840 +        registers[31] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 
   1.841          end
   1.842      else begin
   1.843          if (reg_write_enable_q_w == `TRUE)
   1.844 -          registers[write_idx_w] <= w_result;
   1.845 +          registers[write_idx_w] <= #1 w_result;
   1.846          end
   1.847  end
   1.848  `endif
   1.849 @@ -2647,19 +2693,19 @@
   1.850  begin
   1.851      if (rst_i == `TRUE)
   1.852      begin
   1.853 -        trace_pc_valid <= `FALSE;
   1.854 -        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
   1.855 -        trace_exception <= `FALSE;
   1.856 -        trace_eid <= `LM32_EID_RESET;
   1.857 -        trace_eret <= `FALSE;
   1.858 +        trace_pc_valid <= #1 `FALSE;
   1.859 +        trace_pc <= #1 {`LM32_PC_WIDTH{1'b0}};
   1.860 +        trace_exception <= #1 `FALSE;
   1.861 +        trace_eid <= #1 `LM32_EID_RESET;
   1.862 +        trace_eret <= #1 `FALSE;
   1.863  `ifdef CFG_DEBUG_ENABLED
   1.864 -        trace_bret <= `FALSE;
   1.865 +        trace_bret <= #1 `FALSE;
   1.866  `endif
   1.867 -        pc_c <= `CFG_EBA_RESET/4;
   1.868 +        pc_c <= #1 `CFG_EBA_RESET/4;
   1.869      end
   1.870      else
   1.871      begin
   1.872 -        trace_pc_valid <= `FALSE;
   1.873 +        trace_pc_valid <= #1 `FALSE;
   1.874          // Has an exception occured
   1.875  `ifdef CFG_DEBUG_ENABLED
   1.876          if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
   1.877 @@ -2667,13 +2713,13 @@
   1.878          if (exception_q_w == `TRUE)
   1.879  `endif
   1.880          begin        
   1.881 -            trace_exception <= `TRUE;
   1.882 -            trace_pc_valid <= `TRUE;
   1.883 -            trace_pc <= pc_w;
   1.884 -            trace_eid <= eid_w;
   1.885 +            trace_exception <= #1 `TRUE;
   1.886 +            trace_pc_valid <= #1 `TRUE;
   1.887 +            trace_pc <= #1 pc_w;
   1.888 +            trace_eid <= #1 eid_w;
   1.889          end
   1.890          else
   1.891 -            trace_exception <= `FALSE;
   1.892 +            trace_exception <= #1 `FALSE;
   1.893          
   1.894          if ((valid_w == `TRUE) && (!kill_w))
   1.895          begin
   1.896 @@ -2681,22 +2727,22 @@
   1.897              if (pc_c + 1'b1 != pc_w)
   1.898              begin
   1.899                  // Non-sequential instruction
   1.900 -                trace_pc_valid <= `TRUE;
   1.901 -                trace_pc <= pc_w;
   1.902 +                trace_pc_valid <= #1 `TRUE;
   1.903 +                trace_pc <= #1 pc_w;
   1.904              end
   1.905              // Record PC so we can determine if next instruction is sequential or not
   1.906 -            pc_c <= pc_w;
   1.907 +            pc_c <= #1 pc_w;
   1.908              // Indicate if it was an eret/bret instruction
   1.909 -            trace_eret <= eret_w;
   1.910 +            trace_eret <= #1 eret_w;
   1.911  `ifdef CFG_DEBUG_ENABLED
   1.912 -            trace_bret <= bret_w;
   1.913 +            trace_bret <= #1 bret_w;
   1.914  `endif
   1.915          end
   1.916          else
   1.917          begin
   1.918 -            trace_eret <= `FALSE;
   1.919 +            trace_eret <= #1 `FALSE;
   1.920  `ifdef CFG_DEBUG_ENABLED
   1.921 -            trace_bret <= `FALSE;
   1.922 +            trace_bret <= #1 `FALSE;
   1.923  `endif
   1.924          end
   1.925      end