lm32_dcache.v

changeset 26
73de224304c1
parent 0
cd0b58aa6f83
child 27
d6c693415d59
     1.1 --- a/lm32_dcache.v	Sun Mar 06 21:14:43 2011 +0000
     1.2 +++ b/lm32_dcache.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 @@ -1,18 +1,39 @@
     1.4 -// =============================================================================
     1.5 -//                           COPYRIGHT NOTICE
     1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 -// ALL RIGHTS RESERVED
     1.8 -// This confidential and proprietary software may be used only as authorised by
     1.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 -// The entire notice above must be reproduced on all authorized copies and
    1.11 -// copies may only be made to the extent permitted by a licensing agreement from
    1.12 -// Lattice Semiconductor Corporation.
    1.13 +//   ==================================================================
    1.14 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    1.15 +//   ------------------------------------------------------------------
    1.16 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    1.17 +//   ALL RIGHTS RESERVED 
    1.18 +//   ------------------------------------------------------------------
    1.19 +//
    1.20 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    1.21 +//
    1.22 +//   Permission:
    1.23 +//
    1.24 +//      Lattice Semiconductor grants permission to use this code
    1.25 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    1.26 +//      Open Source License Agreement.  
    1.27 +//
    1.28 +//   Disclaimer:
    1.29  //
    1.30 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.31 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.32 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.33 -// U.S.A                                   email: techsupport@latticesemi.com
    1.34 -// =============================================================================/
    1.35 +//      Lattice Semiconductor provides no warranty regarding the use or
    1.36 +//      functionality of this code. It is the user's responsibility to
    1.37 +//      verify the userís design for consistency and functionality through
    1.38 +//      the use of formal verification methods.
    1.39 +//
    1.40 +//   --------------------------------------------------------------------
    1.41 +//
    1.42 +//                  Lattice Semiconductor Corporation
    1.43 +//                  5555 NE Moore Court
    1.44 +//                  Hillsboro, OR 97214
    1.45 +//                  U.S.A
    1.46 +//
    1.47 +//                  TEL: 1-800-Lattice (USA and Canada)
    1.48 +//                         503-286-8001 (other locations)
    1.49 +//
    1.50 +//                  web: http://www.latticesemi.com/
    1.51 +//                  email: techsupport@latticesemi.com
    1.52 +//
    1.53 +//   --------------------------------------------------------------------
    1.54  //                         FILE DETAILS
    1.55  // Project          : LatticeMico32
    1.56  // File             : lm32_dcache.v
    1.57 @@ -420,11 +441,11 @@
    1.58  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.59  begin
    1.60      if (rst_i == `TRUE)
    1.61 -        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
    1.62 +        refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1};
    1.63      else
    1.64      begin        
    1.65          if (refill_request == `TRUE)
    1.66 -            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
    1.67 +            refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]};
    1.68      end
    1.69  end
    1.70      end 
    1.71 @@ -434,9 +455,9 @@
    1.72  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.73  begin
    1.74      if (rst_i == `TRUE)
    1.75 -        refilling <= `FALSE;
    1.76 +        refilling <= #1 `FALSE;
    1.77      else 
    1.78 -        refilling <= refill;
    1.79 +        refilling <= #1 refill;
    1.80  end
    1.81  
    1.82  // Instruction cache control FSM
    1.83 @@ -444,11 +465,11 @@
    1.84  begin
    1.85      if (rst_i == `TRUE)
    1.86      begin
    1.87 -        state <= `LM32_DC_STATE_FLUSH;
    1.88 -        flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
    1.89 -        refill_request <= `FALSE;
    1.90 -        refill_address <= {`LM32_WORD_WIDTH{1'bx}};
    1.91 -        restart_request <= `FALSE;
    1.92 +        state <= #1 `LM32_DC_STATE_FLUSH;
    1.93 +        flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
    1.94 +        refill_request <= #1 `FALSE;
    1.95 +        refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}};
    1.96 +        restart_request <= #1 `FALSE;
    1.97      end
    1.98      else 
    1.99      begin
   1.100 @@ -458,35 +479,35 @@
   1.101          `LM32_DC_STATE_FLUSH:
   1.102          begin
   1.103              if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
   1.104 -                state <= `LM32_DC_STATE_CHECK;
   1.105 -            flush_set <= flush_set - 1'b1;
   1.106 +                state <= #1 `LM32_DC_STATE_CHECK;
   1.107 +            flush_set <= #1 flush_set - 1'b1;
   1.108          end
   1.109          
   1.110          // Check for cache misses
   1.111          `LM32_DC_STATE_CHECK:
   1.112          begin
   1.113              if (stall_a == `FALSE)
   1.114 -                restart_request <= `FALSE;
   1.115 +                restart_request <= #1 `FALSE;
   1.116              if (miss == `TRUE)
   1.117              begin
   1.118 -                refill_request <= `TRUE;
   1.119 -                refill_address <= address_m;
   1.120 -                state <= `LM32_DC_STATE_REFILL;
   1.121 +                refill_request <= #1 `TRUE;
   1.122 +                refill_address <= #1 address_m;
   1.123 +                state <= #1 `LM32_DC_STATE_REFILL;
   1.124              end
   1.125              else if (dflush == `TRUE)
   1.126 -                state <= `LM32_DC_STATE_FLUSH;
   1.127 +                state <= #1 `LM32_DC_STATE_FLUSH;
   1.128          end
   1.129  
   1.130          // Refill a cache line
   1.131          `LM32_DC_STATE_REFILL:
   1.132          begin
   1.133 -            refill_request <= `FALSE;
   1.134 +            refill_request <= #1 `FALSE;
   1.135              if (refill_ready == `TRUE)
   1.136              begin
   1.137                  if (last_refill == `TRUE)
   1.138                  begin
   1.139 -                    restart_request <= `TRUE;
   1.140 -                    state <= `LM32_DC_STATE_CHECK;
   1.141 +                    restart_request <= #1 `TRUE;
   1.142 +                    state <= #1 `LM32_DC_STATE_CHECK;
   1.143                  end
   1.144              end
   1.145          end
   1.146 @@ -502,7 +523,7 @@
   1.147  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.148  begin
   1.149      if (rst_i == `TRUE)
   1.150 -        refill_offset <= {addr_offset_width{1'b0}};
   1.151 +        refill_offset <= #1 {addr_offset_width{1'b0}};
   1.152      else 
   1.153      begin
   1.154          case (state)
   1.155 @@ -511,14 +532,14 @@
   1.156          `LM32_DC_STATE_CHECK:
   1.157          begin
   1.158              if (miss == `TRUE)
   1.159 -                refill_offset <= {addr_offset_width{1'b0}};
   1.160 +                refill_offset <= #1 {addr_offset_width{1'b0}};
   1.161          end
   1.162  
   1.163          // Refill a cache line
   1.164          `LM32_DC_STATE_REFILL:
   1.165          begin
   1.166              if (refill_ready == `TRUE)
   1.167 -                refill_offset <= refill_offset + 1'b1;
   1.168 +                refill_offset <= #1 refill_offset + 1'b1;
   1.169          end
   1.170          
   1.171          endcase