1.1 --- a/lm32_interrupt.v Sun Mar 06 21:14:43 2011 +0000 1.2 +++ b/lm32_interrupt.v Sat Aug 06 00:02:46 2011 +0100 1.3 @@ -1,18 +1,39 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LatticeMico32 1.56 // File : lm32_interrupt.v 1.57 @@ -199,64 +220,64 @@ 1.58 begin 1.59 if (rst_i == `TRUE) 1.60 begin 1.61 - ie <= `FALSE; 1.62 - eie <= `FALSE; 1.63 + ie <= #1 `FALSE; 1.64 + eie <= #1 `FALSE; 1.65 `ifdef CFG_DEBUG_ENABLED 1.66 - bie <= `FALSE; 1.67 + bie <= #1 `FALSE; 1.68 `endif 1.69 - im <= {interrupts{1'b0}}; 1.70 - ip <= {interrupts{1'b0}}; 1.71 + im <= #1 {interrupts{1'b0}}; 1.72 + ip <= #1 {interrupts{1'b0}}; 1.73 end 1.74 else 1.75 begin 1.76 // Set IP bit when interrupt line is asserted 1.77 - ip <= asserted; 1.78 + ip <= #1 asserted; 1.79 `ifdef CFG_DEBUG_ENABLED 1.80 if (non_debug_exception == `TRUE) 1.81 begin 1.82 // Save and then clear interrupt enable 1.83 - eie <= ie; 1.84 - ie <= `FALSE; 1.85 + eie <= #1 ie; 1.86 + ie <= #1 `FALSE; 1.87 end 1.88 else if (debug_exception == `TRUE) 1.89 begin 1.90 // Save and then clear interrupt enable 1.91 - bie <= ie; 1.92 - ie <= `FALSE; 1.93 + bie <= #1 ie; 1.94 + ie <= #1 `FALSE; 1.95 end 1.96 `else 1.97 if (exception == `TRUE) 1.98 begin 1.99 // Save and then clear interrupt enable 1.100 - eie <= ie; 1.101 - ie <= `FALSE; 1.102 + eie <= #1 ie; 1.103 + ie <= #1 `FALSE; 1.104 end 1.105 `endif 1.106 else if (stall_x == `FALSE) 1.107 begin 1.108 if (eret_q_x == `TRUE) 1.109 // Restore interrupt enable 1.110 - ie <= eie; 1.111 + ie <= #1 eie; 1.112 `ifdef CFG_DEBUG_ENABLED 1.113 else if (bret_q_x == `TRUE) 1.114 // Restore interrupt enable 1.115 - ie <= bie; 1.116 + ie <= #1 bie; 1.117 `endif 1.118 else if (csr_write_enable == `TRUE) 1.119 begin 1.120 // Handle wcsr write 1.121 if (csr == `LM32_CSR_IE) 1.122 begin 1.123 - ie <= csr_write_data[0]; 1.124 - eie <= csr_write_data[1]; 1.125 + ie <= #1 csr_write_data[0]; 1.126 + eie <= #1 csr_write_data[1]; 1.127 `ifdef CFG_DEBUG_ENABLED 1.128 - bie <= csr_write_data[2]; 1.129 + bie <= #1 csr_write_data[2]; 1.130 `endif 1.131 end 1.132 if (csr == `LM32_CSR_IM) 1.133 - im <= csr_write_data[interrupts-1:0]; 1.134 + im <= #1 csr_write_data[interrupts-1:0]; 1.135 if (csr == `LM32_CSR_IP) 1.136 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 1.137 + ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 1.138 end 1.139 end 1.140 end 1.141 @@ -269,61 +290,61 @@ 1.142 begin 1.143 if (rst_i == `TRUE) 1.144 begin 1.145 - ie <= `FALSE; 1.146 - eie <= `FALSE; 1.147 + ie <= #1 `FALSE; 1.148 + eie <= #1 `FALSE; 1.149 `ifdef CFG_DEBUG_ENABLED 1.150 - bie <= `FALSE; 1.151 + bie <= #1 `FALSE; 1.152 `endif 1.153 - ip <= {interrupts{1'b0}}; 1.154 + ip <= #1 {interrupts{1'b0}}; 1.155 end 1.156 else 1.157 begin 1.158 // Set IP bit when interrupt line is asserted 1.159 - ip <= asserted; 1.160 + ip <= #1 asserted; 1.161 `ifdef CFG_DEBUG_ENABLED 1.162 if (non_debug_exception == `TRUE) 1.163 begin 1.164 // Save and then clear interrupt enable 1.165 - eie <= ie; 1.166 - ie <= `FALSE; 1.167 + eie <= #1 ie; 1.168 + ie <= #1 `FALSE; 1.169 end 1.170 else if (debug_exception == `TRUE) 1.171 begin 1.172 // Save and then clear interrupt enable 1.173 - bie <= ie; 1.174 - ie <= `FALSE; 1.175 + bie <= #1 ie; 1.176 + ie <= #1 `FALSE; 1.177 end 1.178 `else 1.179 if (exception == `TRUE) 1.180 begin 1.181 // Save and then clear interrupt enable 1.182 - eie <= ie; 1.183 - ie <= `FALSE; 1.184 + eie <= #1 ie; 1.185 + ie <= #1 `FALSE; 1.186 end 1.187 `endif 1.188 else if (stall_x == `FALSE) 1.189 begin 1.190 if (eret_q_x == `TRUE) 1.191 // Restore interrupt enable 1.192 - ie <= eie; 1.193 + ie <= #1 eie; 1.194 `ifdef CFG_DEBUG_ENABLED 1.195 else if (bret_q_x == `TRUE) 1.196 // Restore interrupt enable 1.197 - ie <= bie; 1.198 + ie <= #1 bie; 1.199 `endif 1.200 else if (csr_write_enable == `TRUE) 1.201 begin 1.202 // Handle wcsr write 1.203 if (csr == `LM32_CSR_IE) 1.204 begin 1.205 - ie <= csr_write_data[0]; 1.206 - eie <= csr_write_data[1]; 1.207 + ie <= #1 csr_write_data[0]; 1.208 + eie <= #1 csr_write_data[1]; 1.209 `ifdef CFG_DEBUG_ENABLED 1.210 - bie <= csr_write_data[2]; 1.211 + bie <= #1 csr_write_data[2]; 1.212 `endif 1.213 end 1.214 if (csr == `LM32_CSR_IP) 1.215 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 1.216 + ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 1.217 end 1.218 end 1.219 end