lm32_jtag.v

changeset 26
73de224304c1
parent 0
cd0b58aa6f83
child 27
d6c693415d59
     1.1 --- a/lm32_jtag.v	Sun Mar 06 21:14:43 2011 +0000
     1.2 +++ b/lm32_jtag.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 @@ -1,18 +1,39 @@
     1.4 -// =============================================================================
     1.5 -//                           COPYRIGHT NOTICE
     1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 -// ALL RIGHTS RESERVED
     1.8 -// This confidential and proprietary software may be used only as authorised by
     1.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 -// The entire notice above must be reproduced on all authorized copies and
    1.11 -// copies may only be made to the extent permitted by a licensing agreement from
    1.12 -// Lattice Semiconductor Corporation.
    1.13 +//   ==================================================================
    1.14 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    1.15 +//   ------------------------------------------------------------------
    1.16 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    1.17 +//   ALL RIGHTS RESERVED 
    1.18 +//   ------------------------------------------------------------------
    1.19 +//
    1.20 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    1.21 +//
    1.22 +//   Permission:
    1.23 +//
    1.24 +//      Lattice Semiconductor grants permission to use this code
    1.25 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    1.26 +//      Open Source License Agreement.  
    1.27 +//
    1.28 +//   Disclaimer:
    1.29  //
    1.30 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.31 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.32 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.33 -// U.S.A                                   email: techsupport@latticesemi.com
    1.34 -// =============================================================================/
    1.35 +//      Lattice Semiconductor provides no warranty regarding the use or
    1.36 +//      functionality of this code. It is the user's responsibility to
    1.37 +//      verify the userís design for consistency and functionality through
    1.38 +//      the use of formal verification methods.
    1.39 +//
    1.40 +//   --------------------------------------------------------------------
    1.41 +//
    1.42 +//                  Lattice Semiconductor Corporation
    1.43 +//                  5555 NE Moore Court
    1.44 +//                  Hillsboro, OR 97214
    1.45 +//                  U.S.A
    1.46 +//
    1.47 +//                  TEL: 1-800-Lattice (USA and Canada)
    1.48 +//                         503-286-8001 (other locations)
    1.49 +//
    1.50 +//                  web: http://www.latticesemi.com/
    1.51 +//                  email: techsupport@latticesemi.com
    1.52 +//
    1.53 +//   --------------------------------------------------------------------
    1.54  //                         FILE DETAILS
    1.55  // Project          : LatticeMico32
    1.56  // File             : lm32_jtag.v
    1.57 @@ -236,9 +257,9 @@
    1.58  always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
    1.59  begin
    1.60  if (rst_i == `TRUE)
    1.61 -  rx_toggle <= 1'b0;
    1.62 +  rx_toggle <= #1 1'b0;
    1.63  else 
    1.64 -  rx_toggle <= ~rx_toggle;
    1.65 +  rx_toggle <= #1 ~rx_toggle;
    1.66  end
    1.67  
    1.68  always @(*)
    1.69 @@ -252,15 +273,15 @@
    1.70  begin
    1.71      if (rst_i == `TRUE)
    1.72      begin
    1.73 -        rx_toggle_r <= 1'b0;
    1.74 -        rx_toggle_r_r <= 1'b0;
    1.75 -        rx_toggle_r_r_r <= 1'b0;
    1.76 +        rx_toggle_r <= #1 1'b0;
    1.77 +        rx_toggle_r_r <= #1 1'b0;
    1.78 +        rx_toggle_r_r_r <= #1 1'b0;
    1.79      end
    1.80      else
    1.81      begin
    1.82 -        rx_toggle_r <= rx_toggle;
    1.83 -        rx_toggle_r_r <= rx_toggle_r;
    1.84 -        rx_toggle_r_r_r <= rx_toggle_r_r;
    1.85 +        rx_toggle_r <= #1 rx_toggle;
    1.86 +        rx_toggle_r_r <= #1 rx_toggle_r;
    1.87 +        rx_toggle_r_r_r <= #1 rx_toggle_r_r;
    1.88      end
    1.89  end
    1.90  
    1.91 @@ -269,24 +290,24 @@
    1.92  begin
    1.93      if (rst_i == `TRUE)
    1.94      begin
    1.95 -        state <= `LM32_JTAG_STATE_READ_COMMAND;
    1.96 -        command <= 4'b0000;
    1.97 -        jtag_reg_d <= 8'h00;
    1.98 +        state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
    1.99 +        command <= #1 4'b0000;
   1.100 +        jtag_reg_d <= #1 8'h00;
   1.101  `ifdef CFG_HW_DEBUG_ENABLED
   1.102 -        processing <= `FALSE;
   1.103 -        jtag_csr_write_enable <= `FALSE;
   1.104 -        jtag_read_enable <= `FALSE;
   1.105 -        jtag_write_enable <= `FALSE;
   1.106 +        processing <= #1 `FALSE;
   1.107 +        jtag_csr_write_enable <= #1 `FALSE;
   1.108 +        jtag_read_enable <= #1 `FALSE;
   1.109 +        jtag_write_enable <= #1 `FALSE;
   1.110  `endif
   1.111  `ifdef CFG_DEBUG_ENABLED
   1.112 -        jtag_break <= `FALSE;
   1.113 -        jtag_reset <= `FALSE;
   1.114 +        jtag_break <= #1 `FALSE;
   1.115 +        jtag_reset <= #1 `FALSE;
   1.116  `endif
   1.117  `ifdef CFG_JTAG_UART_ENABLED                 
   1.118 -        uart_tx_byte <= 8'h00;
   1.119 -        uart_tx_valid <= `FALSE;
   1.120 -        uart_rx_byte <= 8'h00;
   1.121 -        uart_rx_valid <= `FALSE;
   1.122 +        uart_tx_byte <= #1 8'h00;
   1.123 +        uart_tx_valid <= #1 `FALSE;
   1.124 +        uart_rx_byte <= #1 8'h00;
   1.125 +        uart_rx_valid <= #1 `FALSE;
   1.126  `endif
   1.127      end
   1.128      else
   1.129 @@ -298,13 +319,13 @@
   1.130              `LM32_CSR_JTX:
   1.131              begin
   1.132                  // Set flag indicating data is available
   1.133 -                uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
   1.134 -                uart_tx_valid <= `TRUE;
   1.135 +                uart_tx_byte <= #1 csr_write_data[`LM32_BYTE_0_RNG];
   1.136 +                uart_tx_valid <= #1 `TRUE;
   1.137              end
   1.138              `LM32_CSR_JRX:
   1.139              begin
   1.140                  // Clear flag indidicating data has been received
   1.141 -                uart_rx_valid <= `FALSE;
   1.142 +                uart_rx_valid <= #1 `FALSE;
   1.143              end
   1.144              endcase
   1.145          end
   1.146 @@ -313,8 +334,8 @@
   1.147          // When an exception has occured, clear the requests
   1.148          if (exception_q_w == `TRUE)
   1.149          begin
   1.150 -            jtag_break <= `FALSE;
   1.151 -            jtag_reset <= `FALSE;
   1.152 +            jtag_break <= #1 `FALSE;
   1.153 +            jtag_reset <= #1 `FALSE;
   1.154          end
   1.155  `endif
   1.156          case (state)
   1.157 @@ -323,7 +344,7 @@
   1.158              // Wait for rx register to toggle which indicates new data is available
   1.159              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.160              begin
   1.161 -                command <= rx_byte[7:4];                
   1.162 +                command <= #1 rx_byte[7:4];                
   1.163                  case (rx_addr)
   1.164  `ifdef CFG_DEBUG_ENABLED
   1.165                  `LM32_DP:
   1.166 @@ -331,37 +352,37 @@
   1.167                      case (rx_byte[7:4])
   1.168  `ifdef CFG_HW_DEBUG_ENABLED
   1.169                      `LM32_DP_READ_MEMORY:
   1.170 -                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
   1.171 +                        state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
   1.172                      `LM32_DP_READ_SEQUENTIAL:
   1.173                      begin
   1.174 -                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   1.175 -                        state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.176 +                        {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1;
   1.177 +                        state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.178                      end
   1.179                      `LM32_DP_WRITE_MEMORY:
   1.180 -                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
   1.181 +                        state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
   1.182                      `LM32_DP_WRITE_SEQUENTIAL:
   1.183                      begin
   1.184 -                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   1.185 -                        state <= 5;
   1.186 +                        {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1;
   1.187 +                        state <= #1 5;
   1.188                      end
   1.189                      `LM32_DP_WRITE_CSR:
   1.190 -                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
   1.191 +                        state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
   1.192  `endif                    
   1.193                      `LM32_DP_BREAK:
   1.194                      begin
   1.195  `ifdef CFG_JTAG_UART_ENABLED     
   1.196 -                        uart_rx_valid <= `FALSE;    
   1.197 -                        uart_tx_valid <= `FALSE;         
   1.198 +                        uart_rx_valid <= #1 `FALSE;    
   1.199 +                        uart_tx_valid <= #1 `FALSE;         
   1.200  `endif
   1.201 -                        jtag_break <= `TRUE;
   1.202 +                        jtag_break <= #1 `TRUE;
   1.203                      end
   1.204                      `LM32_DP_RESET:
   1.205                      begin
   1.206  `ifdef CFG_JTAG_UART_ENABLED     
   1.207 -                        uart_rx_valid <= `FALSE;    
   1.208 -                        uart_tx_valid <= `FALSE;         
   1.209 +                        uart_rx_valid <= #1 `FALSE;    
   1.210 +                        uart_tx_valid <= #1 `FALSE;         
   1.211  `endif
   1.212 -                        jtag_reset <= `TRUE;
   1.213 +                        jtag_reset <= #1 `TRUE;
   1.214                      end
   1.215                      endcase                               
   1.216                  end
   1.217 @@ -369,13 +390,13 @@
   1.218  `ifdef CFG_JTAG_UART_ENABLED                 
   1.219                  `LM32_TX:
   1.220                  begin
   1.221 -                    uart_rx_byte <= rx_byte;
   1.222 -                    uart_rx_valid <= `TRUE;
   1.223 +                    uart_rx_byte <= #1 rx_byte;
   1.224 +                    uart_rx_valid <= #1 `TRUE;
   1.225                  end                    
   1.226                  `LM32_RX:
   1.227                  begin
   1.228 -                    jtag_reg_d <= uart_tx_byte;
   1.229 -                    uart_tx_valid <= `FALSE;
   1.230 +                    jtag_reg_d <= #1 uart_tx_byte;
   1.231 +                    uart_tx_valid <= #1 `FALSE;
   1.232                  end
   1.233  `endif
   1.234                  default:
   1.235 @@ -388,43 +409,43 @@
   1.236          begin
   1.237              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.238              begin
   1.239 -                jtag_byte_0 <= rx_byte;
   1.240 -                state <= `LM32_JTAG_STATE_READ_BYTE_1;
   1.241 +                jtag_byte_0 <= #1 rx_byte;
   1.242 +                state <= #1 `LM32_JTAG_STATE_READ_BYTE_1;
   1.243              end
   1.244          end
   1.245          `LM32_JTAG_STATE_READ_BYTE_1:
   1.246          begin
   1.247              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.248              begin
   1.249 -                jtag_byte_1 <= rx_byte;
   1.250 -                state <= `LM32_JTAG_STATE_READ_BYTE_2;
   1.251 +                jtag_byte_1 <= #1 rx_byte;
   1.252 +                state <= #1 `LM32_JTAG_STATE_READ_BYTE_2;
   1.253              end
   1.254          end
   1.255          `LM32_JTAG_STATE_READ_BYTE_2:
   1.256          begin
   1.257              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.258              begin
   1.259 -                jtag_byte_2 <= rx_byte;
   1.260 -                state <= `LM32_JTAG_STATE_READ_BYTE_3;
   1.261 +                jtag_byte_2 <= #1 rx_byte;
   1.262 +                state <= #1 `LM32_JTAG_STATE_READ_BYTE_3;
   1.263              end
   1.264          end
   1.265          `LM32_JTAG_STATE_READ_BYTE_3:
   1.266          begin
   1.267              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.268              begin
   1.269 -                jtag_byte_3 <= rx_byte;
   1.270 +                jtag_byte_3 <= #1 rx_byte;
   1.271                  if (command == `LM32_DP_READ_MEMORY)
   1.272 -                    state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.273 +                    state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.274                  else 
   1.275 -                    state <= `LM32_JTAG_STATE_READ_BYTE_4;
   1.276 +                    state <= #1 `LM32_JTAG_STATE_READ_BYTE_4;
   1.277              end
   1.278          end
   1.279          `LM32_JTAG_STATE_READ_BYTE_4:
   1.280          begin
   1.281              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.282              begin
   1.283 -                jtag_byte_4 <= rx_byte;
   1.284 -                state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.285 +                jtag_byte_4 <= #1 rx_byte;
   1.286 +                state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.287              end
   1.288          end
   1.289          `LM32_JTAG_STATE_PROCESS_COMMAND:
   1.290 @@ -433,22 +454,22 @@
   1.291              `LM32_DP_READ_MEMORY,
   1.292              `LM32_DP_READ_SEQUENTIAL:
   1.293              begin
   1.294 -                jtag_read_enable <= `TRUE;
   1.295 -                processing <= `TRUE;
   1.296 -                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   1.297 +                jtag_read_enable <= #1 `TRUE;
   1.298 +                processing <= #1 `TRUE;
   1.299 +                state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   1.300              end
   1.301              `LM32_DP_WRITE_MEMORY,
   1.302              `LM32_DP_WRITE_SEQUENTIAL:
   1.303              begin
   1.304 -                jtag_write_enable <= `TRUE;
   1.305 -                processing <= `TRUE;
   1.306 -                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   1.307 +                jtag_write_enable <= #1 `TRUE;
   1.308 +                processing <= #1 `TRUE;
   1.309 +                state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   1.310              end
   1.311              `LM32_DP_WRITE_CSR:
   1.312              begin
   1.313 -                jtag_csr_write_enable <= `TRUE;
   1.314 -                processing <= `TRUE;
   1.315 -                state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
   1.316 +                jtag_csr_write_enable <= #1 `TRUE;
   1.317 +                processing <= #1 `TRUE;
   1.318 +                state <= #1 `LM32_JTAG_STATE_WAIT_FOR_CSR;
   1.319              end
   1.320              endcase
   1.321          end
   1.322 @@ -456,18 +477,18 @@
   1.323          begin
   1.324              if (jtag_access_complete == `TRUE)
   1.325              begin          
   1.326 -                jtag_read_enable <= `FALSE;
   1.327 -                jtag_reg_d <= jtag_read_data;
   1.328 -                jtag_write_enable <= `FALSE;  
   1.329 -                processing <= `FALSE;
   1.330 -                state <= `LM32_JTAG_STATE_READ_COMMAND;
   1.331 +                jtag_read_enable <= #1 `FALSE;
   1.332 +                jtag_reg_d <= #1 jtag_read_data;
   1.333 +                jtag_write_enable <= #1 `FALSE;  
   1.334 +                processing <= #1 `FALSE;
   1.335 +                state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
   1.336              end
   1.337          end    
   1.338          `LM32_JTAG_STATE_WAIT_FOR_CSR:
   1.339          begin
   1.340 -            jtag_csr_write_enable <= `FALSE;
   1.341 -            processing <= `FALSE;
   1.342 -            state <= `LM32_JTAG_STATE_READ_COMMAND;
   1.343 +            jtag_csr_write_enable <= #1 `FALSE;
   1.344 +            processing <= #1 `FALSE;
   1.345 +            state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
   1.346          end    
   1.347  `endif
   1.348          endcase