lm32_load_store_unit.v

changeset 26
73de224304c1
parent 8
07be9df9fee8
child 27
d6c693415d59
     1.1 --- a/lm32_load_store_unit.v	Sun Mar 06 21:14:43 2011 +0000
     1.2 +++ b/lm32_load_store_unit.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 @@ -1,18 +1,39 @@
     1.4 -// =============================================================================
     1.5 -//                           COPYRIGHT NOTICE
     1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 -// ALL RIGHTS RESERVED
     1.8 -// This confidential and proprietary software may be used only as authorised by
     1.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 -// The entire notice above must be reproduced on all authorized copies and
    1.11 -// copies may only be made to the extent permitted by a licensing agreement from
    1.12 -// Lattice Semiconductor Corporation.
    1.13 +//   ==================================================================
    1.14 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    1.15 +//   ------------------------------------------------------------------
    1.16 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    1.17 +//   ALL RIGHTS RESERVED 
    1.18 +//   ------------------------------------------------------------------
    1.19 +//
    1.20 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    1.21 +//
    1.22 +//   Permission:
    1.23 +//
    1.24 +//      Lattice Semiconductor grants permission to use this code
    1.25 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    1.26 +//      Open Source License Agreement.  
    1.27 +//
    1.28 +//   Disclaimer:
    1.29  //
    1.30 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.31 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.32 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.33 -// U.S.A                                   email: techsupport@latticesemi.com
    1.34 -// =============================================================================/
    1.35 +//      Lattice Semiconductor provides no warranty regarding the use or
    1.36 +//      functionality of this code. It is the user's responsibility to
    1.37 +//      verify the userís design for consistency and functionality through
    1.38 +//      the use of formal verification methods.
    1.39 +//
    1.40 +//   --------------------------------------------------------------------
    1.41 +//
    1.42 +//                  Lattice Semiconductor Corporation
    1.43 +//                  5555 NE Moore Court
    1.44 +//                  Hillsboro, OR 97214
    1.45 +//                  U.S.A
    1.46 +//
    1.47 +//                  TEL: 1-800-Lattice (USA and Canada)
    1.48 +//                         503-286-8001 (other locations)
    1.49 +//
    1.50 +//                  web: http://www.latticesemi.com/
    1.51 +//                  email: techsupport@latticesemi.com
    1.52 +//
    1.53 +//   --------------------------------------------------------------------
    1.54  //                         FILE DETAILS
    1.55  // Project      : LatticeMico32
    1.56  // File         : lm32_load_store_unit.v
    1.57 @@ -302,8 +323,8 @@
    1.58  	    .ResetB                 (rst_i),
    1.59  	    .DataInA                ({32{1'b0}}),
    1.60  	    .DataInB                (dram_store_data_m),
    1.61 -	    .AddressA               (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
    1.62 -	    .AddressB               (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
    1.63 +	    .AddressA               (load_store_address_x[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
    1.64 +	    .AddressB               (load_store_address_m[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
    1.65  	    // .ClockEnA               (!stall_x & (load_x | store_x)),
    1.66  	    .ClockEnA               (!stall_x),
    1.67  	    .ClockEnB               (!stall_m),
    1.68 @@ -322,13 +343,13 @@
    1.69     always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.70       if (rst_i == `TRUE)
    1.71         begin
    1.72 -	  dram_bypass_en <= `FALSE;
    1.73 -	  dram_bypass_data <= 0;
    1.74 +	  dram_bypass_en <= #1 `FALSE;
    1.75 +	  dram_bypass_data <= #1 0;
    1.76         end
    1.77       else
    1.78         begin
    1.79  	  if (stall_x == `FALSE)
    1.80 -	    dram_bypass_data <= dram_store_data_m;
    1.81 +	    dram_bypass_data <= #1 dram_store_data_m;
    1.82  	  
    1.83  	  if (   (stall_m == `FALSE) 
    1.84                && (stall_x == `FALSE)
    1.85 @@ -338,12 +359,12 @@
    1.86  		 )
    1.87  	      && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
    1.88  	     )
    1.89 -	    dram_bypass_en <= `TRUE;
    1.90 +	    dram_bypass_en <= #1 `TRUE;
    1.91  	  else
    1.92  	    if (   (dram_bypass_en == `TRUE)
    1.93  		&& (stall_x == `FALSE)
    1.94  	       )
    1.95 -	      dram_bypass_en <= `FALSE;
    1.96 +	      dram_bypass_en <= #1 `FALSE;
    1.97         end
    1.98     
    1.99     assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
   1.100 @@ -603,26 +624,26 @@
   1.101  begin
   1.102      if (rst_i == `TRUE)
   1.103      begin
   1.104 -        d_cyc_o <= `FALSE;
   1.105 -        d_stb_o <= `FALSE;
   1.106 -        d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
   1.107 -        d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
   1.108 -        d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
   1.109 -        d_we_o <= `FALSE;
   1.110 -        d_cti_o <= `LM32_CTYPE_END;
   1.111 -        d_lock_o <= `FALSE;
   1.112 -        wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.113 -        wb_load_complete <= `FALSE;
   1.114 -        stall_wb_load <= `FALSE;
   1.115 +        d_cyc_o <= #1 `FALSE;
   1.116 +        d_stb_o <= #1 `FALSE;
   1.117 +        d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.118 +        d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.119 +        d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
   1.120 +        d_we_o <= #1 `FALSE;
   1.121 +        d_cti_o <= #1 `LM32_CTYPE_END;
   1.122 +        d_lock_o <= #1 `FALSE;
   1.123 +        wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.124 +        wb_load_complete <= #1 `FALSE;
   1.125 +        stall_wb_load <= #1 `FALSE;
   1.126  `ifdef CFG_DCACHE_ENABLED                
   1.127 -        dcache_refill_ready <= `FALSE;
   1.128 +        dcache_refill_ready <= #1 `FALSE;
   1.129  `endif                
   1.130      end
   1.131      else
   1.132      begin
   1.133  `ifdef CFG_DCACHE_ENABLED 
   1.134          // Refill ready should only be asserted for a single cycle               
   1.135 -        dcache_refill_ready <= `FALSE;
   1.136 +        dcache_refill_ready <= #1 `FALSE;
   1.137  `endif                
   1.138          // Is a Wishbone cycle already in progress?
   1.139          if (d_cyc_o == `TRUE)
   1.140 @@ -634,25 +655,25 @@
   1.141                  if ((dcache_refilling == `TRUE) && (!last_word))
   1.142                  begin
   1.143                      // Fetch next word of cache line    
   1.144 -                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   1.145 +                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   1.146                  end
   1.147                  else
   1.148  `endif                
   1.149                  begin
   1.150                      // Refill/access complete
   1.151 -                    d_cyc_o <= `FALSE;
   1.152 -                    d_stb_o <= `FALSE;
   1.153 -                    d_lock_o <= `FALSE;
   1.154 +                    d_cyc_o <= #1 `FALSE;
   1.155 +                    d_stb_o <= #1 `FALSE;
   1.156 +                    d_lock_o <= #1 `FALSE;
   1.157                  end
   1.158  `ifdef CFG_DCACHE_ENABLED    
   1.159 -                d_cti_o <= next_cycle_type;
   1.160 +                d_cti_o <= #1 next_cycle_type;
   1.161                  // If we are performing a refill, indicate to cache next word of data is ready            
   1.162 -                dcache_refill_ready <= dcache_refilling;
   1.163 +                dcache_refill_ready <= #1 dcache_refilling;
   1.164  `endif
   1.165                  // Register data read from Wishbone interface
   1.166 -                wb_data_m <= d_dat_i;
   1.167 +                wb_data_m <= #1 d_dat_i;
   1.168                  // Don't set when stores complete - otherwise we'll deadlock if load in m stage
   1.169 -                wb_load_complete <= !d_we_o;
   1.170 +                wb_load_complete <= #1 !d_we_o;
   1.171              end
   1.172              // synthesis translate_off            
   1.173              if (d_err_i == `TRUE)
   1.174 @@ -665,13 +686,13 @@
   1.175              if (dcache_refill_request == `TRUE)
   1.176              begin
   1.177                  // Start cache refill
   1.178 -                d_adr_o <= first_address;
   1.179 -                d_cyc_o <= `TRUE;
   1.180 -                d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
   1.181 -                d_stb_o <= `TRUE;                
   1.182 -                d_we_o <= `FALSE;
   1.183 -                d_cti_o <= first_cycle_type;
   1.184 -                //d_lock_o <= `TRUE;
   1.185 +                d_adr_o <= #1 first_address;
   1.186 +                d_cyc_o <= #1 `TRUE;
   1.187 +                d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}};
   1.188 +                d_stb_o <= #1 `TRUE;                
   1.189 +                d_we_o <= #1 `FALSE;
   1.190 +                d_cti_o <= #1 first_cycle_type;
   1.191 +                //d_lock_o <= #1 `TRUE;
   1.192              end
   1.193              else 
   1.194  `endif            
   1.195 @@ -686,13 +707,13 @@
   1.196                      )
   1.197              begin
   1.198                  // Data cache is write through, so all stores go to memory
   1.199 -                d_dat_o <= store_data_m;
   1.200 -                d_adr_o <= load_store_address_m;
   1.201 -                d_cyc_o <= `TRUE;
   1.202 -                d_sel_o <= byte_enable_m;
   1.203 -                d_stb_o <= `TRUE;
   1.204 -                d_we_o <= `TRUE;
   1.205 -                d_cti_o <= `LM32_CTYPE_END;
   1.206 +                d_dat_o <= #1 store_data_m;
   1.207 +                d_adr_o <= #1 load_store_address_m;
   1.208 +                d_cyc_o <= #1 `TRUE;
   1.209 +                d_sel_o <= #1 byte_enable_m;
   1.210 +                d_stb_o <= #1 `TRUE;
   1.211 +                d_we_o <= #1 `TRUE;
   1.212 +                d_cti_o <= #1 `LM32_CTYPE_END;
   1.213              end        
   1.214              else if (   (load_q_m == `TRUE) 
   1.215                       && (wb_select_m == `TRUE) 
   1.216 @@ -701,24 +722,24 @@
   1.217                      )
   1.218              begin
   1.219                  // Read requested address
   1.220 -                stall_wb_load <= `FALSE;
   1.221 -                d_adr_o <= load_store_address_m;
   1.222 -                d_cyc_o <= `TRUE;
   1.223 -                d_sel_o <= byte_enable_m;
   1.224 -                d_stb_o <= `TRUE;
   1.225 -                d_we_o <= `FALSE;
   1.226 -                d_cti_o <= `LM32_CTYPE_END;
   1.227 +                stall_wb_load <= #1 `FALSE;
   1.228 +                d_adr_o <= #1 load_store_address_m;
   1.229 +                d_cyc_o <= #1 `TRUE;
   1.230 +                d_sel_o <= #1 byte_enable_m;
   1.231 +                d_stb_o <= #1 `TRUE;
   1.232 +                d_we_o <= #1 `FALSE;
   1.233 +                d_cti_o <= #1 `LM32_CTYPE_END;
   1.234              end
   1.235          end
   1.236          // Clear load/store complete flag when instruction leaves M stage
   1.237          if (stall_m == `FALSE)
   1.238 -            wb_load_complete <= `FALSE;
   1.239 +            wb_load_complete <= #1 `FALSE;
   1.240          // When a Wishbone load first enters the M stage, we need to stall it
   1.241          if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
   1.242 -            stall_wb_load <= `TRUE;
   1.243 +            stall_wb_load <= #1 `TRUE;
   1.244          // Clear stall request if load instruction is killed
   1.245          if ((kill_m == `TRUE) || (exception_m == `TRUE))
   1.246 -            stall_wb_load <= `FALSE;
   1.247 +            stall_wb_load <= #1 `FALSE;
   1.248      end
   1.249  end
   1.250  
   1.251 @@ -729,39 +750,39 @@
   1.252  begin
   1.253      if (rst_i == `TRUE)
   1.254      begin
   1.255 -        sign_extend_m <= `FALSE;
   1.256 -        size_m <= 2'b00;
   1.257 -        byte_enable_m <= `FALSE;
   1.258 -        store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.259 +        sign_extend_m <= #1 `FALSE;
   1.260 +        size_m <= #1 2'b00;
   1.261 +        byte_enable_m <= #1 `FALSE;
   1.262 +        store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.263  `ifdef CFG_DCACHE_ENABLED
   1.264 -        dcache_select_m <= `FALSE;
   1.265 +        dcache_select_m <= #1 `FALSE;
   1.266  `endif
   1.267  `ifdef CFG_DRAM_ENABLED
   1.268 -        dram_select_m <= `FALSE;
   1.269 +        dram_select_m <= #1 `FALSE;
   1.270  `endif
   1.271  `ifdef CFG_IROM_ENABLED
   1.272 -        irom_select_m <= `FALSE;
   1.273 +        irom_select_m <= #1 `FALSE;
   1.274  `endif
   1.275 -        wb_select_m <= `FALSE;        
   1.276 +        wb_select_m <= #1 `FALSE;        
   1.277      end
   1.278      else
   1.279      begin
   1.280          if (stall_m == `FALSE)
   1.281          begin
   1.282 -            sign_extend_m <= sign_extend_x;
   1.283 -            size_m <= size_x;
   1.284 -            byte_enable_m <= byte_enable_x;    
   1.285 -            store_data_m <= store_data_x;
   1.286 +            sign_extend_m <= #1 sign_extend_x;
   1.287 +            size_m <= #1 size_x;
   1.288 +            byte_enable_m <= #1 byte_enable_x;    
   1.289 +            store_data_m <= #1 store_data_x;
   1.290  `ifdef CFG_DCACHE_ENABLED
   1.291 -            dcache_select_m <= dcache_select_x;
   1.292 +            dcache_select_m <= #1 dcache_select_x;
   1.293  `endif
   1.294  `ifdef CFG_DRAM_ENABLED
   1.295 -            dram_select_m <= dram_select_x;
   1.296 +            dram_select_m <= #1 dram_select_x;
   1.297  `endif
   1.298  `ifdef CFG_IROM_ENABLED
   1.299 -            irom_select_m <= irom_select_x;
   1.300 +            irom_select_m <= #1 irom_select_x;
   1.301  `endif
   1.302 -            wb_select_m <= wb_select_x;
   1.303 +            wb_select_m <= #1 wb_select_x;
   1.304          end
   1.305      end
   1.306  end
   1.307 @@ -771,15 +792,15 @@
   1.308  begin
   1.309      if (rst_i == `TRUE)
   1.310      begin
   1.311 -        size_w <= 2'b00;
   1.312 -        data_w <= {`LM32_WORD_WIDTH{1'b0}};
   1.313 -        sign_extend_w <= `FALSE;
   1.314 +        size_w <= #1 2'b00;
   1.315 +        data_w <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.316 +        sign_extend_w <= #1 `FALSE;
   1.317      end
   1.318      else
   1.319      begin
   1.320 -        size_w <= size_m;
   1.321 -        data_w <= data_m;
   1.322 -        sign_extend_w <= sign_extend_m;
   1.323 +        size_w <= #1 size_m;
   1.324 +        data_w <= #1 data_m;
   1.325 +        sign_extend_w <= #1 sign_extend_m;
   1.326      end
   1.327  end
   1.328