lm32_monitor.v

changeset 26
73de224304c1
parent 22
35dc7ba83714
child 27
d6c693415d59
     1.1 --- a/lm32_monitor.v	Sun Mar 06 21:14:43 2011 +0000
     1.2 +++ b/lm32_monitor.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 @@ -1,18 +1,39 @@
     1.4 -// =============================================================================
     1.5 -//                           COPYRIGHT NOTICE
     1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 -// ALL RIGHTS RESERVED
     1.8 -// This confidential and proprietary software may be used only as authorised by
     1.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 -// The entire notice above must be reproduced on all authorized copies and
    1.11 -// copies may only be made to the extent permitted by a licensing agreement from
    1.12 -// Lattice Semiconductor Corporation.
    1.13 +//   ==================================================================
    1.14 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    1.15 +//   ------------------------------------------------------------------
    1.16 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    1.17 +//   ALL RIGHTS RESERVED 
    1.18 +//   ------------------------------------------------------------------
    1.19 +//
    1.20 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    1.21 +//
    1.22 +//   Permission:
    1.23 +//
    1.24 +//      Lattice Semiconductor grants permission to use this code
    1.25 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    1.26 +//      Open Source License Agreement.  
    1.27 +//
    1.28 +//   Disclaimer:
    1.29  //
    1.30 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.31 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.32 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.33 -// U.S.A                                   email: techsupport@latticesemi.com
    1.34 -// =============================================================================/
    1.35 +//      Lattice Semiconductor provides no warranty regarding the use or
    1.36 +//      functionality of this code. It is the user's responsibility to
    1.37 +//      verify the userís design for consistency and functionality through
    1.38 +//      the use of formal verification methods.
    1.39 +//
    1.40 +//   --------------------------------------------------------------------
    1.41 +//
    1.42 +//                  Lattice Semiconductor Corporation
    1.43 +//                  5555 NE Moore Court
    1.44 +//                  Hillsboro, OR 97214
    1.45 +//                  U.S.A
    1.46 +//
    1.47 +//                  TEL: 1-800-Lattice (USA and Canada)
    1.48 +//                         503-286-8001 (other locations)
    1.49 +//
    1.50 +//                  web: http://www.latticesemi.com/
    1.51 +//                  email: techsupport@latticesemi.com
    1.52 +//
    1.53 +//   --------------------------------------------------------------------
    1.54  //                         FILE DETAILS
    1.55  // Project          : LatticeMico32
    1.56  // File             : lm32_monitor.v
    1.57 @@ -123,10 +144,10 @@
    1.58  begin
    1.59      if (rst_i == `TRUE)
    1.60      begin
    1.61 -        write_enable <= `FALSE;
    1.62 -        MON_ACK_O <= `FALSE;
    1.63 -        MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
    1.64 -        state <= 2'b00;
    1.65 +        write_enable <= #1 `FALSE;
    1.66 +        MON_ACK_O <= #1 `FALSE;
    1.67 +        MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
    1.68 +        state <= #1 2'b00;
    1.69      end
    1.70      else
    1.71      begin
    1.72 @@ -134,33 +155,33 @@
    1.73          2'b01:
    1.74          begin
    1.75              // Output read data to Wishbone
    1.76 -            MON_ACK_O <= `TRUE;
    1.77 -            MON_DAT_O <= data;
    1.78 +            MON_ACK_O <= #1 `TRUE;
    1.79 +            MON_DAT_O <= #1 data;
    1.80              // Sub-word writes are performed using read-modify-write  
    1.81              // as the Lattice EBRs don't support byte enables
    1.82              if (MON_WE_I == `TRUE)
    1.83 -                write_enable <= `TRUE;
    1.84 -            write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
    1.85 -            write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
    1.86 -            write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
    1.87 -            write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
    1.88 -            state <= 2'b10;
    1.89 +                write_enable <= #1 `TRUE;
    1.90 +            write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
    1.91 +            write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
    1.92 +            write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
    1.93 +            write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
    1.94 +            state <= #1 2'b10;
    1.95          end
    1.96          2'b10:
    1.97          begin
    1.98              // Wishbone access occurs in this cycle
    1.99 -            write_enable <= `FALSE;
   1.100 -            MON_ACK_O <= `FALSE;
   1.101 -            MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
   1.102 -            state <= 2'b00;
   1.103 +            write_enable <= #1 `FALSE;
   1.104 +            MON_ACK_O <= #1 `FALSE;
   1.105 +            MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
   1.106 +            state <= #1 2'b00;
   1.107          end
   1.108          default:
   1.109          begin
   1.110 -           write_enable <= `FALSE;
   1.111 -           MON_ACK_O <= `FALSE;
   1.112 +           write_enable <= #1 `FALSE;
   1.113 +           MON_ACK_O <= #1 `FALSE;
   1.114              // Wait for a Wishbone access
   1.115              if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
   1.116 -                state <= 2'b01;
   1.117 +                state <= #1 2'b01;
   1.118          end
   1.119          endcase        
   1.120      end