1.1 --- a/lm32_trace.v Sun Mar 06 21:14:43 2011 +0000 1.2 +++ b/lm32_trace.v Sat Aug 06 00:02:46 2011 +0100 1.3 @@ -1,18 +1,39 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LatticeMico32 1.56 // File : lm32_trace.v 1.57 @@ -24,6 +45,8 @@ 1.58 // : No Change 1.59 // Version : 3.1 1.60 // : No Change 1.61 +// Version : 3.7 1.62 +// : Removed syntax error. 1.63 // ============================================================================= 1.64 1.65 `include "lm32_include.v" 1.66 @@ -123,65 +146,65 @@ 1.67 assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o); 1.68 1.69 initial begin 1.70 - trig_type <= 0; 1.71 - stop_type <= 0; 1.72 - trace_len <= 0; 1.73 - pc_low <= 0; 1.74 - pc_high <= 0; 1.75 - trace_start <= 0; 1.76 - trace_stop <= 0; 1.77 - ack_o <= 0; 1.78 - reg_dat_o <= 0; 1.79 - mem_valid <= 0; 1.80 - started <= 0; 1.81 - capturing <= 0; 1.82 + trig_type <= #1 0; 1.83 + stop_type <= #1 0; 1.84 + trace_len <= #1 0; 1.85 + pc_low <= #1 0; 1.86 + pc_high <= #1 0; 1.87 + trace_start <= #1 0; 1.88 + trace_stop <= #1 0; 1.89 + ack_o <= #1 0; 1.90 + reg_dat_o <= #1 0; 1.91 + mem_valid <= #1 0; 1.92 + started <= #1 0; 1.93 + capturing <= #1 0; 1.94 end 1.95 1.96 // the host side control 1.97 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.98 begin 1.99 if (rst_i == `TRUE) begin 1.100 - trig_type <= 0; 1.101 - trace_stop <= 0; 1.102 - trace_start <= 0; 1.103 - pc_low <= 0; 1.104 - pc_high <= 0; 1.105 - ack_o <= 0; 1.106 + trig_type <= #1 0; 1.107 + trace_stop <= #1 0; 1.108 + trace_start <= #1 0; 1.109 + pc_low <= #1 0; 1.110 + pc_high <= #1 0; 1.111 + ack_o <= #1 0; 1.112 end else begin 1.113 if (stb_i == `TRUE && ack_o == `FALSE) begin 1.114 if (rw_creg) begin // control register access 1.115 - ack_o <= `TRUE; 1.116 + ack_o <= #1 `TRUE; 1.117 if (we_i == `TRUE) begin 1.118 case ({adr_i[11:2],2'b0}) 1.119 // write to trig type 1.120 12'd0: 1.121 begin 1.122 if (sel_i[0]) begin 1.123 - trig_type[4:0] <= dat_i[4:0]; 1.124 + trig_type[4:0] <= #1 dat_i[4:0]; 1.125 end 1.126 if (sel_i[3]) begin 1.127 - trace_start <= dat_i[31]; 1.128 - trace_stop <= dat_i[30]; 1.129 + trace_start <= #1 dat_i[31]; 1.130 + trace_stop <= #1 dat_i[30]; 1.131 end 1.132 end 1.133 12'd8: 1.134 begin 1.135 - if (sel_i[3]) pc_low[31:24] <= dat_i[31:24]; 1.136 - if (sel_i[2]) pc_low[23:16] <= dat_i[23:16]; 1.137 - if (sel_i[1]) pc_low[15:8] <= dat_i[15:8]; 1.138 - if (sel_i[0]) pc_low[7:0] <= dat_i[7:0]; 1.139 + if (sel_i[3]) pc_low[31:24] <= #1 dat_i[31:24]; 1.140 + if (sel_i[2]) pc_low[23:16] <= #1 dat_i[23:16]; 1.141 + if (sel_i[1]) pc_low[15:8] <= #1 dat_i[15:8]; 1.142 + if (sel_i[0]) pc_low[7:0] <= #1 dat_i[7:0]; 1.143 end 1.144 12'd12: 1.145 begin 1.146 - if (sel_i[3]) pc_high[31:24] <= dat_i[31:24]; 1.147 - if (sel_i[2]) pc_high[23:16] <= dat_i[23:16]; 1.148 - if (sel_i[1]) pc_high[15:8] <= dat_i[15:8]; 1.149 - if (sel_i[0]) pc_high[7:0] <= dat_i[7:0]; 1.150 + if (sel_i[3]) pc_high[31:24] <= #1 dat_i[31:24]; 1.151 + if (sel_i[2]) pc_high[23:16] <= #1 dat_i[23:16]; 1.152 + if (sel_i[1]) pc_high[15:8] <= #1 dat_i[15:8]; 1.153 + if (sel_i[0]) pc_high[7:0] <= #1 dat_i[7:0]; 1.154 end 1.155 12'd16: 1.156 begin 1.157 if (sel_i[0])begin 1.158 - stop_type[4:0] <= dat_i[4:0]; 1.159 + stop_type[4:0] <= #1 dat_i[4:0]; 1.160 end 1.161 end 1.162 endcase 1.163 @@ -189,27 +212,27 @@ 1.164 case ({adr_i[11:2],2'b0}) 1.165 // read the trig type 1.166 12'd0: 1.167 - reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 1.168 + reg_dat_o <= #1 {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 1.169 12'd4: 1.170 - reg_dat_o <= trace_len; 1.171 + reg_dat_o <= #1 trace_len; 1.172 12'd8: 1.173 - reg_dat_o <= pc_low; 1.174 + reg_dat_o <= #1 pc_low; 1.175 12'd12: 1.176 - reg_dat_o <= pc_high; 1.177 + reg_dat_o <= #1 pc_high; 1.178 default: 1.179 - reg_dat_o <= {27'b0,stop_type}; 1.180 + reg_dat_o <= #1 {27'b0,stop_type}; 1.181 endcase 1.182 end // else: !if(we_i == `TRUE) 1.183 end else // read / write memory 1.184 if (we_i == `FALSE) begin 1.185 - ack_o <= `TRUE; 1.186 + ack_o <= #1 `TRUE; 1.187 end else 1.188 - ack_o <= `FALSE; 1.189 + ack_o <= #1 `FALSE; 1.190 // not allowed to write to trace memory 1.191 end else begin // if (stb_i == `TRUE) 1.192 - trace_start <= `FALSE; 1.193 - trace_stop <= `FALSE; 1.194 - ack_o <= `FALSE; 1.195 + trace_start <= #1 `FALSE; 1.196 + trace_stop <= #1 `FALSE; 1.197 + ack_o <= #1 `FALSE; 1.198 end // else: !if(stb_i == `TRUE) 1.199 end // else: !if(rst_i == `TRUE) 1.200 end 1.201 @@ -245,31 +268,31 @@ 1.202 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.203 begin 1.204 if (rst_i == `TRUE) begin 1.205 - tstate <= 0; 1.206 - trace_we <= 0; 1.207 - trace_len <= 0; 1.208 - ovrflw <= `FALSE; 1.209 - mem_valid <= 0; 1.210 - started <= 0; 1.211 - capturing <= 0; 1.212 + tstate <= #1 0; 1.213 + trace_we <= #1 0; 1.214 + trace_len <= #1 0; 1.215 + ovrflw <= #1 `FALSE; 1.216 + mem_valid <= #1 0; 1.217 + started <= #1 0; 1.218 + capturing <= #1 0; 1.219 end else begin 1.220 case (tstate) 1.221 3'd0: 1.222 // start capture 1.223 if (trace_start) begin 1.224 - tstate <= 3'd1; 1.225 - mem_valid <= 0; 1.226 - started <= 1; 1.227 + tstate <= #1 3'd1; 1.228 + mem_valid <= #1 0; 1.229 + started <= #1 1; 1.230 end 1.231 3'd1: 1.232 begin 1.233 // wait for trigger 1.234 if (trace_begin) begin 1.235 - capturing <= 1; 1.236 - tstate <= 3'd2; 1.237 - trace_we <= `TRUE; 1.238 - trace_len <= 0; 1.239 - ovrflw <= `FALSE; 1.240 + capturing <= #1 1; 1.241 + tstate <= #1 3'd2; 1.242 + trace_we <= #1 `TRUE; 1.243 + trace_len <= #1 0; 1.244 + ovrflw <= #1 `FALSE; 1.245 end 1.246 end // case: 3'd1 1.247 1.248 @@ -277,18 +300,18 @@ 1.249 begin 1.250 if (trace_pc_valid) begin 1.251 if (trace_len[mem_addr_width]) 1.252 - trace_len <= 0; 1.253 + trace_len <= #1 0; 1.254 else 1.255 - trace_len <= trace_len + 1; 1.256 + trace_len <= #1 trace_len + 1; 1.257 end 1.258 - if (!ovrflw) ovrflw <= trace_len[mem_addr_width]; 1.259 + if (!ovrflw) ovrflw <= #1 trace_len[mem_addr_width]; 1.260 // wait for stop condition 1.261 if (trace_end) begin 1.262 - tstate <= 3'd0; 1.263 - trace_we <= 0; 1.264 - mem_valid <= 1; 1.265 - started <= 0; 1.266 - capturing <= 0; 1.267 + tstate <= #1 3'd0; 1.268 + trace_we <= #1 0; 1.269 + mem_valid <= #1 1; 1.270 + started <= #1 0; 1.271 + capturing <= #1 0; 1.272 end 1.273 end // case: 3'd2 1.274 endcase