1.1 --- a/lm32_include.v Sun Mar 06 21:04:44 2011 +0000 1.2 +++ b/lm32_include.v Sun Mar 06 21:08:02 2011 +0000 1.3 @@ -33,18 +33,18 @@ 1.4 `else 1.5 `define LM32_INCLUDE_V 1.6 1.7 -// (config opts from http://www.reflextor.org/trac/a51/browser/fpga/main/cores/lm32/rtl/lm32_include.v?rev=20) 1.8 // 1.9 // Common configuration options 1.10 // 1.11 1.12 -`define CFG_EBA_RESET 32'h0 1.13 -`define CFG_DEBA_RESET 32'h0 1.14 +`define CFG_EBA_RESET 32'h00000000 1.15 +`define CFG_DEBA_RESET 32'h10000000 1.16 1.17 `define CFG_PL_MULTIPLY_ENABLED 1.18 `define CFG_PL_BARREL_SHIFT_ENABLED 1.19 `define CFG_SIGN_EXTEND_ENABLED 1.20 `define CFG_MC_DIVIDE_ENABLED 1.21 +`define CFG_EBR_POSEDGE_REGISTER_FILE 1.22 1.23 // [found by Milkymist dev'rs] 1.24 // Bug in Xst: 1.25 @@ -52,19 +52,28 @@ 1.26 // CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all 1.27 // Works 100% OK with expensive synthesizers. 1.28 `define CFG_ICACHE_ENABLED 1.29 -`define CFG_ICACHE_ASSOCIATIVITY 2 1.30 -`define CFG_ICACHE_SETS 512 1.31 -`define CFG_ICACHE_BYTES_PER_LINE 4 1.32 +`define CFG_ICACHE_ASSOCIATIVITY 1 1.33 +`define CFG_ICACHE_SETS 256 1.34 +`define CFG_ICACHE_BYTES_PER_LINE 16 1.35 `define CFG_ICACHE_BASE_ADDRESS 32'h0 1.36 `define CFG_ICACHE_LIMIT 32'h7FFF_FFFF 1.37 1.38 `define CFG_DCACHE_ENABLED 1.39 -`define CFG_DCACHE_ASSOCIATIVITY 2 1.40 -`define CFG_DCACHE_SETS 512 1.41 -`define CFG_DCACHE_BYTES_PER_LINE 4 1.42 +`define CFG_DCACHE_ASSOCIATIVITY 1 1.43 +`define CFG_DCACHE_SETS 256 1.44 +`define CFG_DCACHE_BYTES_PER_LINE 16 1.45 `define CFG_DCACHE_BASE_ADDRESS 32'h0 1.46 `define CFG_DCACHE_LIMIT 32'h0FFF_FFFF 1.47 1.48 +// Enable Debugging 1.49 +//`define CFG_JTAG_ENABLED 1.50 +//`define CFG_JTAG_UART_ENABLED 1.51 +//`define CFG_DEBUG_ENABLED 1.52 +//`define CFG_HW_DEBUG_ENABLED 1.53 +//`define CFG_ROM_DEBUG_ENABLED 1.54 +//`define CFG_BREAKPOINTS 32'h0 1.55 +//`define CFG_WATCHPOINTS 32'h0 1.56 + 1.57 // 1.58 // End of common configuration options 1.59 // 1.60 @@ -123,8 +132,8 @@ 1.61 `define LM32_SHIFT_OP_RIGHT 1'b0 1.62 `define LM32_SHIFT_OP_LEFT 1'b1 1.63 1.64 -// Currently always enabled 1.65 -`define CFG_BUS_ERRORS_ENABLED 1.66 +// Bus errors 1.67 +//`define CFG_BUS_ERRORS_ENABLED 1.68 1.69 // Derive macro that indicates whether we have single-stepping or not 1.70 `ifdef CFG_ROM_DEBUG_ENABLED 1.71 @@ -331,9 +340,6 @@ 1.72 // To use a synchronous reset, define this macro as nothing 1.73 `define CFG_RESET_SENSITIVITY 1.74 1.75 -// V.T. Srce 1.76 -`define SRCE 1.77 - 1.78 // Whether to include context registers for debug exceptions 1.79 // in addition to standard exception handling registers 1.80 `define CFG_DEBUG_EXCEPTIONS_ENABLED