jtag_cores.v

changeset 18
cc945f778cd7
parent 17
50bf3061dbff
     1.1 --- a/jtag_cores.v	Sun Mar 06 19:49:17 2011 +0000
     1.2 +++ b/jtag_cores.v	Sun Mar 06 21:03:32 2011 +0000
     1.3 @@ -1,3 +1,5 @@
     1.4 +// Modified by GSI to use simple positive edge clocking and the JTAG capture state
     1.5 +
     1.6  module jtag_cores (
     1.7      input [7:0] reg_d,
     1.8      input [2:0] reg_addr_d,
     1.9 @@ -11,15 +13,19 @@
    1.10  wire tck;
    1.11  wire tdi;
    1.12  wire tdo;
    1.13 +wire capture;
    1.14  wire shift;
    1.15  wire update;
    1.16 +wire e1dr;
    1.17  wire reset;
    1.18  
    1.19  jtag_tap jtag_tap (
    1.20  	.tck(tck),
    1.21  	.tdi(tdi),
    1.22  	.tdo(tdo),
    1.23 +	.capture(capture),
    1.24  	.shift(shift),
    1.25 +	.e1dr(e1dr),
    1.26  	.update(update),
    1.27  	.reset(reset)
    1.28  );
    1.29 @@ -27,26 +33,28 @@
    1.30  reg [10:0] jtag_shift;
    1.31  reg [10:0] jtag_latched;
    1.32  
    1.33 -always @(posedge tck or posedge reset)
    1.34 +always @(posedge tck)
    1.35  begin
    1.36  	if(reset)
    1.37  		jtag_shift <= 11'b0;
    1.38  	else begin
    1.39 -		if(shift)
    1.40 +		if (shift)
    1.41  			jtag_shift <= {tdi, jtag_shift[10:1]};
    1.42 -		else
    1.43 +		else if (capture)
    1.44  			jtag_shift <= {reg_d, reg_addr_d};
    1.45  	end
    1.46  end
    1.47  
    1.48  assign tdo = jtag_shift[0];
    1.49  
    1.50 -always @(posedge reg_update or posedge reset)
    1.51 +always @(posedge tck)
    1.52  begin
    1.53  	if(reset)
    1.54  		jtag_latched <= 11'b0;
    1.55 -	else
    1.56 -		jtag_latched <= jtag_shift;
    1.57 +	else begin
    1.58 +	   if (e1dr)
    1.59 +		   jtag_latched <= jtag_shift;
    1.60 +	end
    1.61  end
    1.62  
    1.63  assign reg_update = update;