lm32_jtag.v

changeset 18
cc945f778cd7
parent 14
54dd95f89113
     1.1 --- a/lm32_jtag.v	Sun Mar 06 19:49:17 2011 +0000
     1.2 +++ b/lm32_jtag.v	Sun Mar 06 21:03:32 2011 +0000
     1.3 @@ -170,13 +170,15 @@
     1.4  // Internal nets and registers 
     1.5  /////////////////////////////////////////////////////
     1.6  
     1.7 -reg rx_toggle;                          // Clock-domain crossing registers
     1.8 -reg rx_toggle_r;                        // Registered version of rx_toggle
     1.9 -reg rx_toggle_r_r;                      // Registered version of rx_toggle_r
    1.10 -reg rx_toggle_r_r_r;                    // Registered version of rx_toggle_r_r
    1.11 +reg rx_update;                          // Clock-domain crossing registers
    1.12 +reg rx_update_r;                        // Registered version of rx_update
    1.13 +reg rx_update_r_r;                      // Registered version of rx_update_r
    1.14 +reg rx_update_r_r_r;                    // Registered version of rx_update_r_r
    1.15  
    1.16 -reg [`LM32_BYTE_RNG] rx_byte;   
    1.17 -reg [2:0] rx_addr;
    1.18 +// These wires come from the JTAG clock domain.
    1.19 +// They have been held unchanged for an entire JTAG clock cycle before the jtag_update toggle flips
    1.20 +wire [`LM32_BYTE_RNG] rx_byte;   
    1.21 +wire [2:0] rx_addr;
    1.22  
    1.23  `ifdef CFG_JTAG_UART_ENABLED                 
    1.24  reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
    1.25 @@ -229,36 +231,26 @@
    1.26  // Sequential Logic
    1.27  /////////////////////////////////////////////////////
    1.28  
    1.29 -// Toggle a flag when a JTAG write occurs
    1.30 - 
    1.31 -always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
    1.32 -begin
    1.33 -if (rst_i == `TRUE)
    1.34 -  rx_toggle <= 1'b0;
    1.35 -else 
    1.36 -  rx_toggle <= ~rx_toggle;
    1.37 -end
    1.38 +assign rx_byte = jtag_reg_q;
    1.39 +assign rx_addr = jtag_reg_addr_q;
    1.40  
    1.41 -always @(*)
    1.42 -begin
    1.43 -    rx_byte = jtag_reg_q;
    1.44 -    rx_addr = jtag_reg_addr_q;
    1.45 -end
    1.46 -
    1.47 -// Clock domain crossing from JTAG clock domain to CPU clock domain
    1.48 +// The JTAG latched jtag_reg[_addr]_q at least one JTCK before jtag_update is raised
    1.49 +// Thus, they are stable (and safe to sample) when jtag_update is high
    1.50  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.51  begin
    1.52      if (rst_i == `TRUE)
    1.53      begin
    1.54 -        rx_toggle_r <= 1'b0;
    1.55 -        rx_toggle_r_r <= 1'b0;
    1.56 -        rx_toggle_r_r_r <= 1'b0;
    1.57 +        rx_update <= 1'b0;
    1.58 +        rx_update_r <= 1'b0;
    1.59 +        rx_update_r_r <= 1'b0;
    1.60 +        rx_update_r_r_r <= 1'b0;
    1.61      end
    1.62      else
    1.63      begin
    1.64 -        rx_toggle_r <= rx_toggle;
    1.65 -        rx_toggle_r_r <= rx_toggle_r;
    1.66 -        rx_toggle_r_r_r <= rx_toggle_r_r;
    1.67 +        rx_update <= jtag_update;
    1.68 +        rx_update_r <= rx_update;
    1.69 +        rx_update_r_r <= rx_update_r;
    1.70 +        rx_update_r_r_r <= rx_update_r_r;
    1.71      end
    1.72  end
    1.73  
    1.74 @@ -319,7 +311,7 @@
    1.75          `LM32_JTAG_STATE_READ_COMMAND:
    1.76          begin
    1.77              // Wait for rx register to toggle which indicates new data is available
    1.78 -            if (rx_toggle_r_r != rx_toggle_r_r_r)
    1.79 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
    1.80              begin
    1.81                  command <= rx_byte[7:4];                
    1.82                  case (rx_addr)
    1.83 @@ -384,7 +376,7 @@
    1.84  `ifdef CFG_HW_DEBUG_ENABLED
    1.85          `LM32_JTAG_STATE_READ_BYTE_0:
    1.86          begin
    1.87 -            if (rx_toggle_r_r != rx_toggle_r_r_r)
    1.88 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
    1.89              begin
    1.90                  jtag_byte_0 <= rx_byte;
    1.91                  state <= `LM32_JTAG_STATE_READ_BYTE_1;
    1.92 @@ -392,7 +384,7 @@
    1.93          end
    1.94          `LM32_JTAG_STATE_READ_BYTE_1:
    1.95          begin
    1.96 -            if (rx_toggle_r_r != rx_toggle_r_r_r)
    1.97 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
    1.98              begin
    1.99                  jtag_byte_1 <= rx_byte;
   1.100                  state <= `LM32_JTAG_STATE_READ_BYTE_2;
   1.101 @@ -400,7 +392,7 @@
   1.102          end
   1.103          `LM32_JTAG_STATE_READ_BYTE_2:
   1.104          begin
   1.105 -            if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.106 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   1.107              begin
   1.108                  jtag_byte_2 <= rx_byte;
   1.109                  state <= `LM32_JTAG_STATE_READ_BYTE_3;
   1.110 @@ -408,7 +400,7 @@
   1.111          end
   1.112          `LM32_JTAG_STATE_READ_BYTE_3:
   1.113          begin
   1.114 -            if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.115 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   1.116              begin
   1.117                  jtag_byte_3 <= rx_byte;
   1.118                  if (command == `LM32_DP_READ_MEMORY)
   1.119 @@ -419,7 +411,7 @@
   1.120          end
   1.121          `LM32_JTAG_STATE_READ_BYTE_4:
   1.122          begin
   1.123 -            if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.124 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   1.125              begin
   1.126                  jtag_byte_4 <= rx_byte;
   1.127                  state <= `LM32_JTAG_STATE_PROCESS_COMMAND;