jtag_cores.v

changeset 0
cd0b58aa6f83
child 14
54dd95f89113
child 26
73de224304c1
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/jtag_cores.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,125 @@
     1.4 +// ============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// ============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : jtag_cores.v
    1.22 +// Title            : Instantiates all IP cores on JTAG chain.
    1.23 +// Dependencies     : system_conf.v
    1.24 +// Version          : 6.0.14
    1.25 +//                  : modified to use jtagconn for LM32,
    1.26 +//                  : all technologies 7/10/07
    1.27 +// Version          : 7.0SP2, 3.0
    1.28 +//                  : No Change
    1.29 +// Version          : 3.1
    1.30 +//                  : No Change
    1.31 +// ============================================================================
    1.32 +
    1.33 +`include "system_conf.v"
    1.34 +
    1.35 +/////////////////////////////////////////////////////
    1.36 +// jtagconn16 Module Definition
    1.37 +/////////////////////////////////////////////////////
    1.38 +
    1.39 +module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
    1.40 +    input  er2_tdo ; 
    1.41 +    output jtck ; 
    1.42 +    output jtdi ; 
    1.43 +    output jshift ; 
    1.44 +    output jupdate ; 
    1.45 +    output jrstn ; 
    1.46 +    output jce2 ; 
    1.47 +    output ip_enable ; 
    1.48 +endmodule
    1.49 +
    1.50 +/////////////////////////////////////////////////////
    1.51 +// Module interface
    1.52 +/////////////////////////////////////////////////////
    1.53 +
    1.54 +(* syn_hier="hard" *) module jtag_cores (
    1.55 +    // ----- Inputs -------
    1.56 +    reg_d,
    1.57 +    reg_addr_d,
    1.58 +    // ----- Outputs -------    
    1.59 +    reg_update,
    1.60 +    reg_q,
    1.61 +    reg_addr_q,
    1.62 +    jtck,
    1.63 +    jrstn
    1.64 +    );
    1.65 +    
    1.66 +/////////////////////////////////////////////////////
    1.67 +// Inputs
    1.68 +/////////////////////////////////////////////////////
    1.69 +
    1.70 +input [7:0] reg_d;
    1.71 +input [2:0] reg_addr_d;
    1.72 +
    1.73 +/////////////////////////////////////////////////////
    1.74 +// Outputs
    1.75 +/////////////////////////////////////////////////////
    1.76 +   
    1.77 +output reg_update;
    1.78 +wire   reg_update;
    1.79 +output [7:0] reg_q;
    1.80 +wire   [7:0] reg_q;
    1.81 +output [2:0] reg_addr_q;
    1.82 +wire   [2:0] reg_addr_q;
    1.83 +
    1.84 +output jtck;
    1.85 +wire   jtck; 	/* synthesis syn_keep=1 */
    1.86 +output jrstn;
    1.87 +wire   jrstn;  /* synthesis syn_keep=1 */	
    1.88 +
    1.89 +/////////////////////////////////////////////////////
    1.90 +// Instantiations
    1.91 +/////////////////////////////////////////////////////
    1.92 +
    1.93 +wire jtdi;          /* synthesis syn_keep=1 */
    1.94 +wire er2_tdo2;      /* synthesis syn_keep=1 */
    1.95 +wire jshift;        /* synthesis syn_keep=1 */
    1.96 +wire jupdate;       /* synthesis syn_keep=1 */
    1.97 +wire jce2;          /* synthesis syn_keep=1 */
    1.98 +wire ip_enable;     /* synthesis syn_keep=1 */
    1.99 +    
   1.100 +(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
   1.101 +    .er2_tdo        (er2_tdo2),
   1.102 +    .jtck           (jtck),
   1.103 +    .jtdi           (jtdi),
   1.104 +    .jshift         (jshift),
   1.105 +    .jupdate        (jupdate),
   1.106 +    .jrstn          (jrstn),
   1.107 +    .jce2           (jce2),
   1.108 +    .ip_enable      (ip_enable)
   1.109 +);
   1.110 +    
   1.111 +(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
   1.112 +    .JTCK           (jtck),
   1.113 +    .JTDI           (jtdi),
   1.114 +    .JTDO2          (er2_tdo2),
   1.115 +    .JSHIFT         (jshift),
   1.116 +    .JUPDATE        (jupdate),
   1.117 +    .JRSTN          (jrstn),
   1.118 +    .JCE2           (jce2),
   1.119 +    .JTAGREG_ENABLE (ip_enable),
   1.120 +    .CONTROL_DATAN  (),
   1.121 +    .REG_UPDATE     (reg_update),
   1.122 +    .REG_D          (reg_d),
   1.123 +    .REG_ADDR_D     (reg_addr_d),
   1.124 +    .REG_Q          (reg_q),
   1.125 +    .REG_ADDR_Q     (reg_addr_q)
   1.126 +    );
   1.127 +    
   1.128 +endmodule