jtag_lm32.v

changeset 0
cd0b58aa6f83
child 26
73de224304c1
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/jtag_lm32.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,200 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : jtag_lm32.v
    1.22 +// Title            : JTAG data register for LM32 CPU debug interface
    1.23 +// Version          : 6.0.13
    1.24 +//                  : Initial Release
    1.25 +// Version          : 7.0SP2, 3.0
    1.26 +//                  : No Change
    1.27 +// Version          : 3.1
    1.28 +//                  : No Change
    1.29 +// =============================================================================
    1.30 +
    1.31 +/////////////////////////////////////////////////////
    1.32 +// Module interface
    1.33 +/////////////////////////////////////////////////////
    1.34 +
    1.35 +module jtag_lm32 (
    1.36 +	input JTCK,
    1.37 +	input JTDI,
    1.38 +	output JTDO2,
    1.39 +	input JSHIFT,
    1.40 +	input JUPDATE,
    1.41 +	input JRSTN,
    1.42 +	input JCE2,
    1.43 +	input JTAGREG_ENABLE,
    1.44 +	input CONTROL_DATAN,
    1.45 +	output REG_UPDATE,
    1.46 +	input [7:0] REG_D,
    1.47 +	input [2:0] REG_ADDR_D,
    1.48 +	output [7:0] REG_Q,
    1.49 +	output [2:0] REG_ADDR_Q
    1.50 +	);
    1.51 +
    1.52 +/////////////////////////////////////////////////////
    1.53 +// Internal nets and registers 
    1.54 +/////////////////////////////////////////////////////
    1.55 +
    1.56 +wire [9:0] tdibus;
    1.57 +
    1.58 +/////////////////////////////////////////////////////
    1.59 +// Instantiations
    1.60 +/////////////////////////////////////////////////////
    1.61 +   
    1.62 +TYPEA DATA_BIT0 (
    1.63 +    .CLK(JTCK),
    1.64 +    .RESET_N(JRSTN),
    1.65 +    .CLKEN(clk_enable),
    1.66 +    .TDI(JTDI),
    1.67 +    .TDO(tdibus[0]),
    1.68 +    .DATA_OUT(REG_Q[0]),
    1.69 +    .DATA_IN(REG_D[0]),
    1.70 +    .CAPTURE_DR(captureDr),
    1.71 +    .UPDATE_DR(JUPDATE)
    1.72 +    );
    1.73 +
    1.74 +TYPEA DATA_BIT1 (
    1.75 +    .CLK(JTCK),
    1.76 +    .RESET_N(JRSTN),
    1.77 +    .CLKEN(clk_enable),
    1.78 +    .TDI(tdibus[0]),
    1.79 +    .TDO(tdibus[1]),
    1.80 +    .DATA_OUT(REG_Q[1]),
    1.81 +    .DATA_IN(REG_D[1]),
    1.82 +    .CAPTURE_DR(captureDr),
    1.83 +    .UPDATE_DR(JUPDATE)
    1.84 +    );
    1.85 +
    1.86 +TYPEA DATA_BIT2 (
    1.87 +    .CLK(JTCK),
    1.88 +    .RESET_N(JRSTN),
    1.89 +    .CLKEN(clk_enable),
    1.90 +    .TDI(tdibus[1]),
    1.91 +    .TDO(tdibus[2]),
    1.92 +    .DATA_OUT(REG_Q[2]),
    1.93 +    .DATA_IN(REG_D[2]),
    1.94 +    .CAPTURE_DR(captureDr),
    1.95 +    .UPDATE_DR(JUPDATE)
    1.96 +    );
    1.97 +
    1.98 +TYPEA DATA_BIT3 (
    1.99 +    .CLK(JTCK),
   1.100 +    .RESET_N(JRSTN),
   1.101 +    .CLKEN(clk_enable),
   1.102 +    .TDI(tdibus[2]),
   1.103 +    .TDO(tdibus[3]),
   1.104 +    .DATA_OUT(REG_Q[3]),
   1.105 +    .DATA_IN(REG_D[3]),
   1.106 +    .CAPTURE_DR(captureDr),
   1.107 +    .UPDATE_DR(JUPDATE)
   1.108 +    );
   1.109 +
   1.110 +TYPEA DATA_BIT4 (
   1.111 +    .CLK(JTCK),
   1.112 +    .RESET_N(JRSTN),
   1.113 +    .CLKEN(clk_enable),
   1.114 +    .TDI(tdibus[3]),
   1.115 +    .TDO(tdibus[4]),
   1.116 +    .DATA_OUT(REG_Q[4]),
   1.117 +    .DATA_IN(REG_D[4]),
   1.118 +    .CAPTURE_DR(captureDr),
   1.119 +    .UPDATE_DR(JUPDATE)
   1.120 +    );
   1.121 +
   1.122 +TYPEA DATA_BIT5 (
   1.123 +    .CLK(JTCK),
   1.124 +    .RESET_N(JRSTN),
   1.125 +    .CLKEN(clk_enable),
   1.126 +    .TDI(tdibus[4]),
   1.127 +    .TDO(tdibus[5]),
   1.128 +    .DATA_OUT(REG_Q[5]),
   1.129 +    .DATA_IN(REG_D[5]),
   1.130 +    .CAPTURE_DR(captureDr),
   1.131 +    .UPDATE_DR(JUPDATE)
   1.132 +    );
   1.133 +
   1.134 +TYPEA DATA_BIT6 (
   1.135 +    .CLK(JTCK),
   1.136 +    .RESET_N(JRSTN),
   1.137 +    .CLKEN(clk_enable),
   1.138 +    .TDI(tdibus[5]),
   1.139 +    .TDO(tdibus[6]),
   1.140 +    .DATA_OUT(REG_Q[6]),
   1.141 +    .DATA_IN(REG_D[6]),
   1.142 +    .CAPTURE_DR(captureDr),
   1.143 +    .UPDATE_DR(JUPDATE)
   1.144 +    );
   1.145 +
   1.146 +TYPEA DATA_BIT7 (
   1.147 +    .CLK(JTCK),
   1.148 +    .RESET_N(JRSTN),
   1.149 +    .CLKEN(clk_enable),
   1.150 +    .TDI(tdibus[6]),
   1.151 +    .TDO(tdibus[7]),
   1.152 +    .DATA_OUT(REG_Q[7]),
   1.153 +    .DATA_IN(REG_D[7]),
   1.154 +    .CAPTURE_DR(captureDr),
   1.155 +    .UPDATE_DR(JUPDATE)
   1.156 +    );
   1.157 +
   1.158 +TYPEA ADDR_BIT0 (
   1.159 +    .CLK(JTCK),
   1.160 +    .RESET_N(JRSTN),
   1.161 +    .CLKEN(clk_enable),
   1.162 +    .TDI(tdibus[7]),
   1.163 +    .TDO(tdibus[8]),
   1.164 +    .DATA_OUT(REG_ADDR_Q[0]),
   1.165 +    .DATA_IN(REG_ADDR_D[0]),
   1.166 +    .CAPTURE_DR(captureDr),
   1.167 +    .UPDATE_DR(JUPDATE)
   1.168 +    );
   1.169 +
   1.170 +TYPEA ADDR_BIT1 (
   1.171 +    .CLK(JTCK),
   1.172 +    .RESET_N(JRSTN),
   1.173 +    .CLKEN(clk_enable),
   1.174 +    .TDI(tdibus[8]),
   1.175 +    .TDO(tdibus[9]),
   1.176 +    .DATA_OUT(REG_ADDR_Q[1]),
   1.177 +    .DATA_IN(REG_ADDR_D[1]),
   1.178 +    .CAPTURE_DR(captureDr),
   1.179 +    .UPDATE_DR(JUPDATE)
   1.180 +    );
   1.181 +
   1.182 +TYPEA ADDR_BIT2 (
   1.183 +    .CLK(JTCK),
   1.184 +    .RESET_N(JRSTN),
   1.185 +    .CLKEN(clk_enable),
   1.186 +    .TDI(tdibus[9]),
   1.187 +    .TDO(JTDO2),
   1.188 +    .DATA_OUT(REG_ADDR_Q[2]),
   1.189 +    .DATA_IN(REG_ADDR_D[2]),
   1.190 +    .CAPTURE_DR(captureDr),
   1.191 +    .UPDATE_DR(JUPDATE)
   1.192 +    );
   1.193 +
   1.194 +/////////////////////////////////////////////////////
   1.195 +// Combinational logic
   1.196 +/////////////////////////////////////////////////////
   1.197 +
   1.198 +assign clk_enable = JTAGREG_ENABLE & JCE2;
   1.199 +assign captureDr = !JSHIFT & JCE2;
   1.200 +// JCE2 is only active during shift
   1.201 +assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
   1.202 + 
   1.203 +endmodule