lm32_cpu.v

changeset 0
cd0b58aa6f83
child 8
07be9df9fee8
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/lm32_cpu.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,2732 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : lm32_cpu.v
    1.22 +// Title            : Top-level of CPU.
    1.23 +// Dependencies     : lm32_include.v
    1.24 +//
    1.25 +// Version 3.4
    1.26 +// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
    1.27 +//    never serviced.
    1.28 +//    
    1.29 +// Version 3.3
    1.30 +// 1. Feature: Support for memory that is tightly coupled to processor core, and 
    1.31 +//    has a single-cycle access latency (same as caches). Instruction port has
    1.32 +//    access to a dedicated physically-mapped memory. Data port has access to
    1.33 +//    a dedicated physically-mapped memory. In order to be able to manipulate
    1.34 +//    values in both these memories via the debugger, these memories also
    1.35 +//    interface with the data port of LM32.
    1.36 +// 2. Feature: Extended Configuration Register
    1.37 +// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
    1.38 +//    Verilog.
    1.39 +//
    1.40 +// Version 3.2
    1.41 +// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
    1.42 +//    hang. At the same time CPU fails to register data bus error exception. Bug
    1.43 +//    is caused because (a) data bus error exception occurs after load/store has
    1.44 +//    passed X stage and next sequential instruction (e.g., brk) is already in X
    1.45 +//    stage, and (b) data bus error exception had lower priority than, say, brk
    1.46 +//    exception.
    1.47 +// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
    1.48 +//    invalid location, CPU will fail to register data bus error exception. The
    1.49 +//    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
    1.50 +//    until load/store has completed.
    1.51 +// 3. Feature: Enable precise identification of load/store that causes seg fault.
    1.52 +// 4. SYNC resets used for register file when implemented in EBRs.
    1.53 +//
    1.54 +// Version 3.1
    1.55 +// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
    1.56 +//    instead of distributed memory by enabling the option in LM32 GUI. 
    1.57 +// 2. Feature: LM32 also adds a static branch predictor to improve branch 
    1.58 +//    performance. All immediate-based forward-pointing branches are predicted 
    1.59 +//    not-taken. All immediate-based backward-pointing branches are predicted taken.
    1.60 +// 
    1.61 +// Version 7.0SP2, 3.0
    1.62 +// No Change
    1.63 +//
    1.64 +// Version 6.1.17
    1.65 +// Initial Release
    1.66 +// =============================================================================
    1.67 +
    1.68 +`include "lm32_include.v"
    1.69 +
    1.70 +/////////////////////////////////////////////////////
    1.71 +// Module interface
    1.72 +/////////////////////////////////////////////////////
    1.73 +
    1.74 +module lm32_cpu (
    1.75 +    // ----- Inputs -------
    1.76 +    clk_i,
    1.77 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
    1.78 +    clk_n_i,
    1.79 +`endif    
    1.80 +    rst_i,
    1.81 +    // From external devices
    1.82 +`ifdef CFG_INTERRUPTS_ENABLED
    1.83 +    interrupt_n,
    1.84 +`endif
    1.85 +    // From user logic
    1.86 +`ifdef CFG_USER_ENABLED
    1.87 +    user_result,
    1.88 +    user_complete,
    1.89 +`endif     
    1.90 +`ifdef CFG_JTAG_ENABLED
    1.91 +    // From JTAG
    1.92 +    jtag_clk,
    1.93 +    jtag_update, 
    1.94 +    jtag_reg_q,
    1.95 +    jtag_reg_addr_q,
    1.96 +`endif
    1.97 +`ifdef CFG_IWB_ENABLED
    1.98 +    // Instruction Wishbone master
    1.99 +    I_DAT_I,
   1.100 +    I_ACK_I,
   1.101 +    I_ERR_I,
   1.102 +    I_RTY_I,
   1.103 +`endif
   1.104 +    // Data Wishbone master
   1.105 +    D_DAT_I,
   1.106 +    D_ACK_I,
   1.107 +    D_ERR_I,
   1.108 +    D_RTY_I,
   1.109 +    // ----- Outputs -------
   1.110 +`ifdef CFG_TRACE_ENABLED
   1.111 +    trace_pc,
   1.112 +    trace_pc_valid,
   1.113 +    trace_exception,
   1.114 +    trace_eid,
   1.115 +    trace_eret,
   1.116 +`ifdef CFG_DEBUG_ENABLED
   1.117 +    trace_bret,
   1.118 +`endif
   1.119 +`endif
   1.120 +`ifdef CFG_JTAG_ENABLED
   1.121 +    jtag_reg_d,
   1.122 +    jtag_reg_addr_d,
   1.123 +`endif
   1.124 +`ifdef CFG_USER_ENABLED    
   1.125 +    user_valid,
   1.126 +    user_opcode,
   1.127 +    user_operand_0,
   1.128 +    user_operand_1,
   1.129 +`endif    
   1.130 +`ifdef CFG_IWB_ENABLED
   1.131 +    // Instruction Wishbone master
   1.132 +    I_DAT_O,
   1.133 +    I_ADR_O,
   1.134 +    I_CYC_O,
   1.135 +    I_SEL_O,
   1.136 +    I_STB_O,
   1.137 +    I_WE_O,
   1.138 +    I_CTI_O,
   1.139 +    I_LOCK_O,
   1.140 +    I_BTE_O,
   1.141 +`endif
   1.142 +    // Data Wishbone master
   1.143 +    D_DAT_O,
   1.144 +    D_ADR_O,
   1.145 +    D_CYC_O,
   1.146 +    D_SEL_O,
   1.147 +    D_STB_O,
   1.148 +    D_WE_O,
   1.149 +    D_CTI_O,
   1.150 +    D_LOCK_O,
   1.151 +    D_BTE_O
   1.152 +    );
   1.153 +
   1.154 +/////////////////////////////////////////////////////
   1.155 +// Parameters
   1.156 +/////////////////////////////////////////////////////
   1.157 +
   1.158 +parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
   1.159 +`ifdef CFG_DEBUG_ENABLED
   1.160 +parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
   1.161 +`endif
   1.162 +
   1.163 +`ifdef CFG_ICACHE_ENABLED
   1.164 +parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   1.165 +parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
   1.166 +parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   1.167 +parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
   1.168 +parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
   1.169 +`else
   1.170 +parameter icache_associativity = 1;    
   1.171 +parameter icache_sets = 512;                      
   1.172 +parameter icache_bytes_per_line = 16;  
   1.173 +parameter icache_base_address = 0;      
   1.174 +parameter icache_limit = 0;                    
   1.175 +`endif
   1.176 +
   1.177 +`ifdef CFG_DCACHE_ENABLED
   1.178 +parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   1.179 +parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
   1.180 +parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   1.181 +parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
   1.182 +parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
   1.183 +`else
   1.184 +parameter dcache_associativity = 1;    
   1.185 +parameter dcache_sets = 512;                      
   1.186 +parameter dcache_bytes_per_line = 16;  
   1.187 +parameter dcache_base_address = 0;      
   1.188 +parameter dcache_limit = 0;                    
   1.189 +`endif
   1.190 +
   1.191 +`ifdef CFG_DEBUG_ENABLED
   1.192 +parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
   1.193 +`else
   1.194 +parameter watchpoints = 0;
   1.195 +`endif
   1.196 +`ifdef CFG_ROM_DEBUG_ENABLED
   1.197 +parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
   1.198 +`else
   1.199 +parameter breakpoints = 0;
   1.200 +`endif
   1.201 +
   1.202 +`ifdef CFG_INTERRUPTS_ENABLED
   1.203 +parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
   1.204 +`else
   1.205 +parameter interrupts = 0;
   1.206 +`endif
   1.207 +
   1.208 +/////////////////////////////////////////////////////
   1.209 +// Inputs
   1.210 +/////////////////////////////////////////////////////
   1.211 +
   1.212 +input clk_i;                                    // Clock
   1.213 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   1.214 +input clk_n_i;                                  // Inverted clock
   1.215 +`endif    
   1.216 +input rst_i;                                    // Reset
   1.217 +
   1.218 +`ifdef CFG_INTERRUPTS_ENABLED
   1.219 +input [`LM32_INTERRUPT_RNG] interrupt_n;        // Interrupt pins, active-low
   1.220 +`endif
   1.221 +
   1.222 +`ifdef CFG_USER_ENABLED
   1.223 +input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
   1.224 +input user_complete;                            // User-defined instruction execution is complete
   1.225 +`endif    
   1.226 +
   1.227 +`ifdef CFG_JTAG_ENABLED
   1.228 +input jtag_clk;                                 // JTAG clock
   1.229 +input jtag_update;                              // JTAG state machine is in data register update state
   1.230 +input [`LM32_BYTE_RNG] jtag_reg_q;              
   1.231 +input [2:0] jtag_reg_addr_q;
   1.232 +`endif
   1.233 +
   1.234 +`ifdef CFG_IWB_ENABLED
   1.235 +input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
   1.236 +input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
   1.237 +input I_ERR_I;                                  // Instruction Wishbone interface error
   1.238 +input I_RTY_I;                                  // Instruction Wishbone interface retry
   1.239 +`endif
   1.240 +
   1.241 +input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
   1.242 +input D_ACK_I;                                  // Data Wishbone interface acknowledgement
   1.243 +input D_ERR_I;                                  // Data Wishbone interface error
   1.244 +input D_RTY_I;                                  // Data Wishbone interface retry
   1.245 +
   1.246 +/////////////////////////////////////////////////////
   1.247 +// Outputs
   1.248 +/////////////////////////////////////////////////////
   1.249 +
   1.250 +`ifdef CFG_TRACE_ENABLED
   1.251 +output [`LM32_PC_RNG] trace_pc;                 // PC to trace
   1.252 +reg    [`LM32_PC_RNG] trace_pc;
   1.253 +output trace_pc_valid;                          // Indicates that a new trace PC is valid
   1.254 +reg    trace_pc_valid;
   1.255 +output trace_exception;                         // Indicates an exception has occured
   1.256 +reg    trace_exception;
   1.257 +output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
   1.258 +reg    [`LM32_EID_RNG] trace_eid;
   1.259 +output trace_eret;                              // Indicates an eret instruction has been executed
   1.260 +reg    trace_eret;
   1.261 +`ifdef CFG_DEBUG_ENABLED
   1.262 +output trace_bret;                              // Indicates a bret instruction has been executed
   1.263 +reg    trace_bret;
   1.264 +`endif
   1.265 +`endif
   1.266 +
   1.267 +`ifdef CFG_JTAG_ENABLED
   1.268 +output [`LM32_BYTE_RNG] jtag_reg_d;
   1.269 +wire   [`LM32_BYTE_RNG] jtag_reg_d;
   1.270 +output [2:0] jtag_reg_addr_d;
   1.271 +wire   [2:0] jtag_reg_addr_d;
   1.272 +`endif
   1.273 +
   1.274 +`ifdef CFG_USER_ENABLED
   1.275 +output user_valid;                              // Indicates if user_opcode is valid
   1.276 +wire   user_valid;
   1.277 +output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
   1.278 +reg    [`LM32_USER_OPCODE_RNG] user_opcode;
   1.279 +output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
   1.280 +wire   [`LM32_WORD_RNG] user_operand_0;
   1.281 +output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
   1.282 +wire   [`LM32_WORD_RNG] user_operand_1;
   1.283 +`endif
   1.284 +
   1.285 +`ifdef CFG_IWB_ENABLED
   1.286 +output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
   1.287 +wire   [`LM32_WORD_RNG] I_DAT_O;
   1.288 +output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
   1.289 +wire   [`LM32_WORD_RNG] I_ADR_O;
   1.290 +output I_CYC_O;                                 // Instruction Wishbone interface cycle
   1.291 +wire   I_CYC_O;
   1.292 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
   1.293 +wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
   1.294 +output I_STB_O;                                 // Instruction Wishbone interface strobe
   1.295 +wire   I_STB_O;
   1.296 +output I_WE_O;                                  // Instruction Wishbone interface write enable
   1.297 +wire   I_WE_O;
   1.298 +output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
   1.299 +wire   [`LM32_CTYPE_RNG] I_CTI_O;
   1.300 +output I_LOCK_O;                                // Instruction Wishbone interface lock bus
   1.301 +wire   I_LOCK_O;
   1.302 +output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
   1.303 +wire   [`LM32_BTYPE_RNG] I_BTE_O;
   1.304 +`endif
   1.305 +
   1.306 +output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
   1.307 +wire   [`LM32_WORD_RNG] D_DAT_O;
   1.308 +output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
   1.309 +wire   [`LM32_WORD_RNG] D_ADR_O;
   1.310 +output D_CYC_O;                                 // Data Wishbone interface cycle
   1.311 +wire   D_CYC_O;
   1.312 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
   1.313 +wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
   1.314 +output D_STB_O;                                 // Data Wishbone interface strobe
   1.315 +wire   D_STB_O;
   1.316 +output D_WE_O;                                  // Data Wishbone interface write enable
   1.317 +wire   D_WE_O;
   1.318 +output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
   1.319 +wire   [`LM32_CTYPE_RNG] D_CTI_O;
   1.320 +output D_LOCK_O;                                // Date Wishbone interface lock bus
   1.321 +wire   D_LOCK_O;
   1.322 +output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
   1.323 +wire   [`LM32_BTYPE_RNG] D_BTE_O;
   1.324 +
   1.325 +/////////////////////////////////////////////////////
   1.326 +// Internal nets and registers 
   1.327 +/////////////////////////////////////////////////////
   1.328 +
   1.329 +// Pipeline registers
   1.330 +
   1.331 +`ifdef LM32_CACHE_ENABLED
   1.332 +reg valid_a;                                    // Instruction in A stage is valid
   1.333 +`endif
   1.334 +reg valid_f;                                    // Instruction in F stage is valid
   1.335 +reg valid_d;                                    // Instruction in D stage is valid
   1.336 +reg valid_x;                                    // Instruction in X stage is valid
   1.337 +reg valid_m;                                    // Instruction in M stage is valid
   1.338 +reg valid_w;                                    // Instruction in W stage is valid
   1.339 +   
   1.340 +wire q_x;
   1.341 +wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
   1.342 +wire load_d;                                    // Indicates a load instruction
   1.343 +reg load_x;                                     
   1.344 +reg load_m;
   1.345 +wire load_q_x;
   1.346 +wire store_q_x;
   1.347 +wire store_d;                                   // Indicates a store instruction
   1.348 +reg store_x;
   1.349 +reg store_m;
   1.350 +wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
   1.351 +reg [`LM32_SIZE_RNG] size_x;
   1.352 +wire branch_d;                                  // Indicates a branch instruction
   1.353 +wire branch_predict_d;                          // Indicates a branch is predicted
   1.354 +wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
   1.355 +wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
   1.356 +wire [`LM32_PC_RNG] branch_target_d;
   1.357 +wire bi_unconditional;
   1.358 +wire bi_conditional;
   1.359 +reg branch_x;                                   
   1.360 +reg branch_predict_x;
   1.361 +reg branch_predict_taken_x;
   1.362 +reg branch_m;
   1.363 +reg branch_predict_m;
   1.364 +reg branch_predict_taken_m;
   1.365 +wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
   1.366 +wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
   1.367 +wire branch_reg_d;                              // Branch to register or immediate
   1.368 +wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
   1.369 +reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
   1.370 +reg [`LM32_PC_RNG] branch_target_m;
   1.371 +wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
   1.372 +wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
   1.373 +
   1.374 +wire x_result_sel_csr_d;                        // Select X stage result from CSRs
   1.375 +reg x_result_sel_csr_x;
   1.376 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   1.377 +wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
   1.378 +reg x_result_sel_mc_arith_x;
   1.379 +`endif
   1.380 +`ifdef LM32_NO_BARREL_SHIFT    
   1.381 +wire x_result_sel_shift_d;                      // Select X stage result from shifter
   1.382 +reg x_result_sel_shift_x;
   1.383 +`endif
   1.384 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.385 +wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
   1.386 +reg x_result_sel_sext_x;
   1.387 +`endif
   1.388 +wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
   1.389 +reg x_result_sel_logic_x;
   1.390 +`ifdef CFG_USER_ENABLED
   1.391 +wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
   1.392 +reg x_result_sel_user_x;
   1.393 +`endif
   1.394 +wire x_result_sel_add_d;                        // Select X stage result from adder
   1.395 +reg x_result_sel_add_x;
   1.396 +wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
   1.397 +reg m_result_sel_compare_x;
   1.398 +reg m_result_sel_compare_m;
   1.399 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.400 +wire m_result_sel_shift_d;                      // Select M stage result from shifter
   1.401 +reg m_result_sel_shift_x;
   1.402 +reg m_result_sel_shift_m;
   1.403 +`endif
   1.404 +wire w_result_sel_load_d;                       // Select W stage result from load/store unit
   1.405 +reg w_result_sel_load_x;
   1.406 +reg w_result_sel_load_m;
   1.407 +reg w_result_sel_load_w;
   1.408 +`ifdef CFG_PL_MULTIPLY_ENABLED
   1.409 +wire w_result_sel_mul_d;                        // Select W stage result from multiplier
   1.410 +reg w_result_sel_mul_x;
   1.411 +reg w_result_sel_mul_m;
   1.412 +reg w_result_sel_mul_w;
   1.413 +`endif
   1.414 +wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
   1.415 +reg x_bypass_enable_x;                          
   1.416 +wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
   1.417 +reg m_bypass_enable_x;                          
   1.418 +reg m_bypass_enable_m;
   1.419 +wire sign_extend_d;                             // Whether to sign-extend or zero-extend
   1.420 +reg sign_extend_x;
   1.421 +wire write_enable_d;                            // Register file write enable
   1.422 +reg write_enable_x;
   1.423 +wire write_enable_q_x;
   1.424 +reg write_enable_m;
   1.425 +wire write_enable_q_m;
   1.426 +reg write_enable_w;
   1.427 +wire write_enable_q_w;
   1.428 +wire read_enable_0_d;                           // Register file read enable 0
   1.429 +wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
   1.430 +wire read_enable_1_d;                           // Register file read enable 1
   1.431 +wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
   1.432 +wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
   1.433 +reg [`LM32_REG_IDX_RNG] write_idx_x;            
   1.434 +reg [`LM32_REG_IDX_RNG] write_idx_m;
   1.435 +reg [`LM32_REG_IDX_RNG] write_idx_w;
   1.436 +wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
   1.437 +reg  [`LM32_CSR_RNG] csr_x;                  
   1.438 +wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
   1.439 +reg [`LM32_CONDITION_RNG] condition_x;          
   1.440 +`ifdef CFG_DEBUG_ENABLED
   1.441 +wire break_d;                                   // Indicates a break instruction
   1.442 +reg break_x;                                    
   1.443 +`endif
   1.444 +wire scall_d;                                   // Indicates a scall instruction
   1.445 +reg scall_x;    
   1.446 +wire eret_d;                                    // Indicates an eret instruction
   1.447 +reg eret_x;
   1.448 +wire eret_q_x;
   1.449 +reg eret_m;
   1.450 +`ifdef CFG_TRACE_ENABLED
   1.451 +reg eret_w;
   1.452 +`endif
   1.453 +`ifdef CFG_DEBUG_ENABLED
   1.454 +wire bret_d;                                    // Indicates a bret instruction
   1.455 +reg bret_x;
   1.456 +wire bret_q_x;
   1.457 +reg bret_m;
   1.458 +`ifdef CFG_TRACE_ENABLED
   1.459 +reg bret_w;
   1.460 +`endif
   1.461 +`endif
   1.462 +wire csr_write_enable_d;                        // CSR write enable
   1.463 +reg csr_write_enable_x;
   1.464 +wire csr_write_enable_q_x;
   1.465 +`ifdef CFG_USER_ENABLED
   1.466 +wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
   1.467 +`endif
   1.468 +
   1.469 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.470 +wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
   1.471 +reg bus_error_x;
   1.472 +reg data_bus_error_exception_m;
   1.473 +reg [`LM32_PC_RNG] memop_pc_w;
   1.474 +`endif
   1.475 +
   1.476 +reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
   1.477 +reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
   1.478 +reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
   1.479 +reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
   1.480 +reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
   1.481 +
   1.482 +reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
   1.483 +reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
   1.484 +reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
   1.485 +reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
   1.486 +reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
   1.487 +
   1.488 +// To/from register file
   1.489 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   1.490 +reg [`LM32_WORD_RNG] reg_data_live_0;          
   1.491 +reg [`LM32_WORD_RNG] reg_data_live_1;  
   1.492 +reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
   1.493 +reg [`LM32_WORD_RNG] reg_data_buf_0;
   1.494 +reg [`LM32_WORD_RNG] reg_data_buf_1;
   1.495 +`endif
   1.496 +`ifdef LM32_EBR_REGISTER_FILE
   1.497 +`else
   1.498 +reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
   1.499 +`endif
   1.500 +wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
   1.501 +wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
   1.502 +reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
   1.503 +reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
   1.504 +wire reg_write_enable_q_w;
   1.505 +
   1.506 +reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
   1.507 +
   1.508 +wire stall_a;                                   // Stall instruction in A pipeline stage
   1.509 +wire stall_f;                                   // Stall instruction in F pipeline stage
   1.510 +wire stall_d;                                   // Stall instruction in D pipeline stage
   1.511 +wire stall_x;                                   // Stall instruction in X pipeline stage
   1.512 +wire stall_m;                                   // Stall instruction in M pipeline stage
   1.513 +
   1.514 +// To/from adder
   1.515 +wire adder_op_d;                                // Whether to add or subtract
   1.516 +reg adder_op_x;                                 
   1.517 +reg adder_op_x_n;                               // Inverted version of adder_op_x
   1.518 +wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
   1.519 +wire adder_overflow_x;                          // Whether a signed overflow occured
   1.520 +wire adder_carry_n_x;                           // Whether a carry was generated
   1.521 +
   1.522 +// To/from logical operations unit
   1.523 +wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
   1.524 +reg [`LM32_LOGIC_OP_RNG] logic_op_x;            
   1.525 +wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
   1.526 +
   1.527 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.528 +// From sign-extension unit
   1.529 +wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
   1.530 +wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
   1.531 +wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
   1.532 +`endif
   1.533 +
   1.534 +// To/from shifter
   1.535 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.536 +`ifdef CFG_ROTATE_ENABLED
   1.537 +wire rotate_d;                                  // Whether we should rotate or shift
   1.538 +reg rotate_x;                                    
   1.539 +`endif
   1.540 +wire direction_d;                               // Which direction to shift in
   1.541 +reg direction_x;                                        
   1.542 +reg direction_m;
   1.543 +wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
   1.544 +`endif
   1.545 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.546 +wire shift_left_d;                              // Indicates whether to perform a left shift or not
   1.547 +wire shift_left_q_d;
   1.548 +wire shift_right_d;                             // Indicates whether to perform a right shift or not
   1.549 +wire shift_right_q_d;
   1.550 +`endif
   1.551 +`ifdef LM32_NO_BARREL_SHIFT
   1.552 +wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
   1.553 +`endif
   1.554 +
   1.555 +// To/from multiplier
   1.556 +`ifdef LM32_MULTIPLY_ENABLED
   1.557 +wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
   1.558 +`endif
   1.559 +`ifdef CFG_MC_MULTIPLY_ENABLED
   1.560 +wire multiply_d;                                // Indicates whether to perform a multiply or not
   1.561 +wire multiply_q_d;
   1.562 +`endif
   1.563 +
   1.564 +// To/from divider
   1.565 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.566 +wire divide_d;                                  // Indicates whether to perform a divider or not
   1.567 +wire divide_q_d;
   1.568 +wire modulus_d;
   1.569 +wire modulus_q_d;
   1.570 +wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
   1.571 +`endif
   1.572 +
   1.573 +// To from multi-cycle arithmetic unit
   1.574 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   1.575 +wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
   1.576 +wire [`LM32_WORD_RNG] mc_result_x;
   1.577 +`endif
   1.578 +
   1.579 +// From CSRs
   1.580 +`ifdef CFG_INTERRUPTS_ENABLED
   1.581 +wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
   1.582 +`endif
   1.583 +wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
   1.584 +wire [`LM32_WORD_RNG] cfg2;                     // Extended Configuration CSR
   1.585 +`ifdef CFG_CYCLE_COUNTER_ENABLED
   1.586 +reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
   1.587 +`endif
   1.588 +reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
   1.589 +
   1.590 +// To/from instruction unit
   1.591 +wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
   1.592 +wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
   1.593 +wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
   1.594 +wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
   1.595 +wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
   1.596 +`ifdef CFG_TRACE_ENABLED
   1.597 +reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
   1.598 +`endif
   1.599 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   1.600 +wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
   1.601 +`endif
   1.602 +//pragma attribute instruction_d preserve_signal true
   1.603 +//pragma attribute instruction_d preserve_driver true
   1.604 +wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
   1.605 +`ifdef CFG_ICACHE_ENABLED
   1.606 +wire iflush;                                    // Flush instruction cache
   1.607 +wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
   1.608 +wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
   1.609 +wire icache_refill_request;                     // Request to refill instruction cache
   1.610 +wire icache_refilling;                          // Indicates the instruction cache is being refilled
   1.611 +`endif
   1.612 +`ifdef CFG_IROM_ENABLED
   1.613 +wire [`LM32_WORD_RNG] irom_store_data_m;        // Store data to instruction ROM
   1.614 +wire [`LM32_WORD_RNG] irom_address_xm;          // Address to instruction ROM from load-store unit
   1.615 +wire [`LM32_WORD_RNG] irom_data_m;              // Load data from instruction ROM
   1.616 +wire irom_we_xm;                                // Indicates data needs to be written to instruction ROM
   1.617 +wire irom_stall_request_x;                      // Indicates D stage needs to be stalled on a store to instruction ROM
   1.618 +`endif
   1.619 +
   1.620 +// To/from load/store unit
   1.621 +`ifdef CFG_DCACHE_ENABLED
   1.622 +wire dflush_x;                                  // Flush data cache    
   1.623 +reg dflush_m;                                    
   1.624 +wire dcache_stall_request;                      // Stall pipeline because data cache is busy
   1.625 +wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
   1.626 +wire dcache_refill_request;                     // Request to refill data cache
   1.627 +wire dcache_refilling;                          // Indicates the data cache is being refilled
   1.628 +`endif
   1.629 +wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
   1.630 +wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
   1.631 +
   1.632 +// To/from JTAG interface
   1.633 +`ifdef CFG_JTAG_ENABLED
   1.634 +`ifdef CFG_JTAG_UART_ENABLED
   1.635 +wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
   1.636 +wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
   1.637 +`endif
   1.638 +`ifdef CFG_HW_DEBUG_ENABLED
   1.639 +wire jtag_csr_write_enable;                     // Debugger CSR write enable
   1.640 +wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
   1.641 +wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
   1.642 +wire jtag_read_enable;                          
   1.643 +wire [`LM32_BYTE_RNG] jtag_read_data;
   1.644 +wire jtag_write_enable;
   1.645 +wire [`LM32_BYTE_RNG] jtag_write_data;
   1.646 +wire [`LM32_WORD_RNG] jtag_address;
   1.647 +wire jtag_access_complete;
   1.648 +`endif
   1.649 +`ifdef CFG_DEBUG_ENABLED
   1.650 +wire jtag_break;                                // Request from debugger to raise a breakpoint
   1.651 +`endif
   1.652 +`endif
   1.653 +
   1.654 +// Hazzard detection
   1.655 +wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
   1.656 +wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
   1.657 +wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
   1.658 +wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
   1.659 +wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
   1.660 +wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
   1.661 +
   1.662 +// Control flow
   1.663 +wire cmp_zero;                                  // Result of comparison is zero
   1.664 +wire cmp_negative;                              // Result of comparison is negative
   1.665 +wire cmp_overflow;                              // Comparison produced an overflow
   1.666 +wire cmp_carry_n;                               // Comparison produced a carry, inverted
   1.667 +reg condition_met_x;                            // Condition of branch instruction is met
   1.668 +reg condition_met_m;
   1.669 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   1.670 +wire branch_taken_x;                            // Branch is taken in X stage
   1.671 +`endif
   1.672 +wire branch_taken_m;                            // Branch is taken in M stage
   1.673 +
   1.674 +wire kill_f;                                    // Kill instruction in F stage
   1.675 +wire kill_d;                                    // Kill instruction in D stage
   1.676 +wire kill_x;                                    // Kill instruction in X stage
   1.677 +wire kill_m;                                    // Kill instruction in M stage
   1.678 +wire kill_w;                                    // Kill instruction in W stage
   1.679 +
   1.680 +reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
   1.681 +`ifdef CFG_DEBUG_ENABLED
   1.682 +reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
   1.683 +`endif
   1.684 +reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
   1.685 +`ifdef CFG_TRACE_ENABLED
   1.686 +reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
   1.687 +reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
   1.688 +`endif
   1.689 +
   1.690 +`ifdef CFG_DEBUG_ENABLED
   1.691 +`ifdef LM32_SINGLE_STEP_ENABLED
   1.692 +wire dc_ss;                                     // Is single-step enabled
   1.693 +`endif
   1.694 +wire dc_re;                                     // Remap all exceptions
   1.695 +wire exception_x;                               // An exception occured in the X stage
   1.696 +reg exception_m;                                // An instruction that caused an exception is in the M stage
   1.697 +wire debug_exception_x;                         // Indicates if a debug exception has occured
   1.698 +reg debug_exception_m;
   1.699 +reg debug_exception_w;
   1.700 +wire debug_exception_q_w;
   1.701 +wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
   1.702 +reg non_debug_exception_m;
   1.703 +reg non_debug_exception_w;
   1.704 +wire non_debug_exception_q_w;
   1.705 +`else
   1.706 +wire exception_x;                               // Indicates if a debug exception has occured
   1.707 +reg exception_m;
   1.708 +reg exception_w;
   1.709 +wire exception_q_w;
   1.710 +`endif
   1.711 +
   1.712 +`ifdef CFG_DEBUG_ENABLED
   1.713 +`ifdef CFG_JTAG_ENABLED
   1.714 +wire reset_exception;                           // Indicates if a reset exception has occured
   1.715 +`endif
   1.716 +`endif
   1.717 +`ifdef CFG_INTERRUPTS_ENABLED
   1.718 +wire interrupt_exception;                       // Indicates if an interrupt exception has occured
   1.719 +`endif
   1.720 +`ifdef CFG_DEBUG_ENABLED
   1.721 +wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
   1.722 +wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
   1.723 +`endif
   1.724 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.725 +wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
   1.726 +wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
   1.727 +`endif
   1.728 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.729 +wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
   1.730 +`endif
   1.731 +wire system_call_exception;                     // Indicates if a system call exception has occured
   1.732 +
   1.733 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.734 +reg data_bus_error_seen;                        // Indicates if a data bus error was seen
   1.735 +`endif
   1.736 +
   1.737 +/////////////////////////////////////////////////////
   1.738 +// Functions
   1.739 +/////////////////////////////////////////////////////
   1.740 +
   1.741 +`include "lm32_functions.v"
   1.742 +
   1.743 +/////////////////////////////////////////////////////
   1.744 +// Instantiations
   1.745 +///////////////////////////////////////////////////// 
   1.746 +
   1.747 +// Instruction unit
   1.748 +lm32_instruction_unit #(
   1.749 +    .associativity          (icache_associativity),
   1.750 +    .sets                   (icache_sets),
   1.751 +    .bytes_per_line         (icache_bytes_per_line),
   1.752 +    .base_address           (icache_base_address),
   1.753 +    .limit                  (icache_limit)
   1.754 +  ) instruction_unit (
   1.755 +    // ----- Inputs -------
   1.756 +    .clk_i                  (clk_i),
   1.757 +    .rst_i                  (rst_i),
   1.758 +    // From pipeline
   1.759 +    .stall_a                (stall_a),
   1.760 +    .stall_f                (stall_f),
   1.761 +    .stall_d                (stall_d),
   1.762 +    .stall_x                (stall_x),
   1.763 +    .stall_m                (stall_m),
   1.764 +    .valid_f                (valid_f),
   1.765 +    .valid_d                (valid_d),
   1.766 +    .kill_f                 (kill_f),
   1.767 +    .branch_predict_taken_d (branch_predict_taken_d),
   1.768 +    .branch_predict_address_d (branch_predict_address_d),
   1.769 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   1.770 +    .branch_taken_x         (branch_taken_x),
   1.771 +    .branch_target_x        (branch_target_x),
   1.772 +`endif
   1.773 +    .exception_m            (exception_m),
   1.774 +    .branch_taken_m         (branch_taken_m),
   1.775 +    .branch_mispredict_taken_m (branch_mispredict_taken_m),
   1.776 +    .branch_target_m        (branch_target_m),
   1.777 +`ifdef CFG_ICACHE_ENABLED
   1.778 +    .iflush                 (iflush),
   1.779 +`endif
   1.780 +`ifdef CFG_IROM_ENABLED
   1.781 +    .irom_store_data_m      (irom_store_data_m),
   1.782 +    .irom_address_xm        (irom_address_xm),
   1.783 +    .irom_we_xm             (irom_we_xm),
   1.784 +`endif
   1.785 +`ifdef CFG_DCACHE_ENABLED
   1.786 +    .dcache_restart_request (dcache_restart_request),
   1.787 +    .dcache_refill_request  (dcache_refill_request),
   1.788 +    .dcache_refilling       (dcache_refilling),
   1.789 +`endif        
   1.790 +`ifdef CFG_IWB_ENABLED
   1.791 +    // From Wishbone
   1.792 +    .i_dat_i                (I_DAT_I),
   1.793 +    .i_ack_i                (I_ACK_I),
   1.794 +    .i_err_i                (I_ERR_I),
   1.795 +    .i_rty_i                (I_RTY_I),
   1.796 +`endif
   1.797 +`ifdef CFG_HW_DEBUG_ENABLED
   1.798 +    .jtag_read_enable       (jtag_read_enable),
   1.799 +    .jtag_write_enable      (jtag_write_enable),
   1.800 +    .jtag_write_data        (jtag_write_data),
   1.801 +    .jtag_address           (jtag_address),
   1.802 +`endif
   1.803 +    // ----- Outputs -------
   1.804 +    // To pipeline
   1.805 +    .pc_f                   (pc_f),
   1.806 +    .pc_d                   (pc_d),
   1.807 +    .pc_x                   (pc_x),
   1.808 +    .pc_m                   (pc_m),
   1.809 +    .pc_w                   (pc_w),
   1.810 +`ifdef CFG_ICACHE_ENABLED
   1.811 +    .icache_stall_request   (icache_stall_request),
   1.812 +    .icache_restart_request (icache_restart_request),
   1.813 +    .icache_refill_request  (icache_refill_request),
   1.814 +    .icache_refilling       (icache_refilling),
   1.815 +`endif
   1.816 +`ifdef CFG_IROM_ENABLED
   1.817 +    .irom_data_m            (irom_data_m),
   1.818 +`endif
   1.819 +`ifdef CFG_IWB_ENABLED
   1.820 +    // To Wishbone
   1.821 +    .i_dat_o                (I_DAT_O),
   1.822 +    .i_adr_o                (I_ADR_O),
   1.823 +    .i_cyc_o                (I_CYC_O),
   1.824 +    .i_sel_o                (I_SEL_O),
   1.825 +    .i_stb_o                (I_STB_O),
   1.826 +    .i_we_o                 (I_WE_O),
   1.827 +    .i_cti_o                (I_CTI_O),
   1.828 +    .i_lock_o               (I_LOCK_O),
   1.829 +    .i_bte_o                (I_BTE_O),
   1.830 +`endif
   1.831 +`ifdef CFG_HW_DEBUG_ENABLED
   1.832 +    .jtag_read_data         (jtag_read_data),
   1.833 +    .jtag_access_complete   (jtag_access_complete),
   1.834 +`endif
   1.835 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.836 +    .bus_error_d            (bus_error_d),
   1.837 +`endif
   1.838 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   1.839 +    .instruction_f          (instruction_f),
   1.840 +`endif
   1.841 +    .instruction_d          (instruction_d)
   1.842 +    );
   1.843 +
   1.844 +// Instruction decoder
   1.845 +lm32_decoder decoder (
   1.846 +    // ----- Inputs -------
   1.847 +    .instruction            (instruction_d),
   1.848 +    // ----- Outputs -------
   1.849 +    .d_result_sel_0         (d_result_sel_0_d),
   1.850 +    .d_result_sel_1         (d_result_sel_1_d),
   1.851 +    .x_result_sel_csr       (x_result_sel_csr_d),
   1.852 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   1.853 +    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
   1.854 +`endif
   1.855 +`ifdef LM32_NO_BARREL_SHIFT    
   1.856 +    .x_result_sel_shift     (x_result_sel_shift_d),
   1.857 +`endif
   1.858 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.859 +    .x_result_sel_sext      (x_result_sel_sext_d),
   1.860 +`endif    
   1.861 +    .x_result_sel_logic     (x_result_sel_logic_d),
   1.862 +`ifdef CFG_USER_ENABLED
   1.863 +    .x_result_sel_user      (x_result_sel_user_d),
   1.864 +`endif
   1.865 +    .x_result_sel_add       (x_result_sel_add_d),
   1.866 +    .m_result_sel_compare   (m_result_sel_compare_d),
   1.867 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.868 +    .m_result_sel_shift     (m_result_sel_shift_d),  
   1.869 +`endif    
   1.870 +    .w_result_sel_load      (w_result_sel_load_d),
   1.871 +`ifdef CFG_PL_MULTIPLY_ENABLED
   1.872 +    .w_result_sel_mul       (w_result_sel_mul_d),
   1.873 +`endif
   1.874 +    .x_bypass_enable        (x_bypass_enable_d),
   1.875 +    .m_bypass_enable        (m_bypass_enable_d),
   1.876 +    .read_enable_0          (read_enable_0_d),
   1.877 +    .read_idx_0             (read_idx_0_d),
   1.878 +    .read_enable_1          (read_enable_1_d),
   1.879 +    .read_idx_1             (read_idx_1_d),
   1.880 +    .write_enable           (write_enable_d),
   1.881 +    .write_idx              (write_idx_d),
   1.882 +    .immediate              (immediate_d),
   1.883 +    .branch_offset          (branch_offset_d),
   1.884 +    .load                   (load_d),
   1.885 +    .store                  (store_d),
   1.886 +    .size                   (size_d),
   1.887 +    .sign_extend            (sign_extend_d),
   1.888 +    .adder_op               (adder_op_d),
   1.889 +    .logic_op               (logic_op_d),
   1.890 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.891 +    .direction              (direction_d),
   1.892 +`endif
   1.893 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.894 +    .shift_left             (shift_left_d),
   1.895 +    .shift_right            (shift_right_d),
   1.896 +`endif
   1.897 +`ifdef CFG_MC_MULTIPLY_ENABLED
   1.898 +    .multiply               (multiply_d),
   1.899 +`endif
   1.900 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.901 +    .divide                 (divide_d),
   1.902 +    .modulus                (modulus_d),
   1.903 +`endif
   1.904 +    .branch                 (branch_d),
   1.905 +    .bi_unconditional       (bi_unconditional),
   1.906 +    .bi_conditional         (bi_conditional),
   1.907 +    .branch_reg             (branch_reg_d),
   1.908 +    .condition              (condition_d),
   1.909 +`ifdef CFG_DEBUG_ENABLED
   1.910 +    .break_opcode           (break_d),
   1.911 +`endif
   1.912 +    .scall                  (scall_d),
   1.913 +    .eret                   (eret_d),
   1.914 +`ifdef CFG_DEBUG_ENABLED
   1.915 +    .bret                   (bret_d),
   1.916 +`endif
   1.917 +`ifdef CFG_USER_ENABLED
   1.918 +    .user_opcode            (user_opcode_d),
   1.919 +`endif
   1.920 +    .csr_write_enable       (csr_write_enable_d)
   1.921 +    ); 
   1.922 +
   1.923 +// Load/store unit       
   1.924 +lm32_load_store_unit #(
   1.925 +    .associativity          (dcache_associativity),
   1.926 +    .sets                   (dcache_sets),
   1.927 +    .bytes_per_line         (dcache_bytes_per_line),
   1.928 +    .base_address           (dcache_base_address),
   1.929 +    .limit                  (dcache_limit)
   1.930 +  ) load_store_unit (
   1.931 +    // ----- Inputs -------
   1.932 +    .clk_i                  (clk_i),
   1.933 +    .rst_i                  (rst_i),
   1.934 +    // From pipeline
   1.935 +    .stall_a                (stall_a),
   1.936 +    .stall_x                (stall_x),
   1.937 +    .stall_m                (stall_m),
   1.938 +    .kill_x                 (kill_x),
   1.939 +    .kill_m                 (kill_m),
   1.940 +    .exception_m            (exception_m),
   1.941 +    .store_operand_x        (store_operand_x),
   1.942 +    .load_store_address_x   (adder_result_x),
   1.943 +    .load_store_address_m   (operand_m),
   1.944 +    .load_store_address_w   (operand_w[1:0]),
   1.945 +    .load_x                 (load_x),
   1.946 +    .store_x                (store_x),
   1.947 +    .load_q_x               (load_q_x),
   1.948 +    .store_q_x              (store_q_x),
   1.949 +    .load_q_m               (load_q_m),
   1.950 +    .store_q_m              (store_q_m),
   1.951 +    .sign_extend_x          (sign_extend_x),
   1.952 +    .size_x                 (size_x),
   1.953 +`ifdef CFG_DCACHE_ENABLED
   1.954 +    .dflush                 (dflush_m),
   1.955 +`endif
   1.956 +`ifdef CFG_IROM_ENABLED
   1.957 +    .irom_data_m            (irom_data_m),
   1.958 +`endif
   1.959 +    // From Wishbone
   1.960 +    .d_dat_i                (D_DAT_I),
   1.961 +    .d_ack_i                (D_ACK_I),
   1.962 +    .d_err_i                (D_ERR_I),
   1.963 +    .d_rty_i                (D_RTY_I),
   1.964 +    // ----- Outputs -------
   1.965 +    // To pipeline
   1.966 +`ifdef CFG_DCACHE_ENABLED
   1.967 +    .dcache_refill_request  (dcache_refill_request),
   1.968 +    .dcache_restart_request (dcache_restart_request),
   1.969 +    .dcache_stall_request   (dcache_stall_request),
   1.970 +    .dcache_refilling       (dcache_refilling),
   1.971 +`endif    
   1.972 +`ifdef CFG_IROM_ENABLED
   1.973 +    .irom_store_data_m      (irom_store_data_m),
   1.974 +    .irom_address_xm        (irom_address_xm),
   1.975 +    .irom_we_xm             (irom_we_xm),
   1.976 +    .irom_stall_request_x   (irom_stall_request_x),
   1.977 +`endif
   1.978 +    .load_data_w            (load_data_w),
   1.979 +    .stall_wb_load          (stall_wb_load),
   1.980 +    // To Wishbone
   1.981 +    .d_dat_o                (D_DAT_O),
   1.982 +    .d_adr_o                (D_ADR_O),
   1.983 +    .d_cyc_o                (D_CYC_O),
   1.984 +    .d_sel_o                (D_SEL_O),
   1.985 +    .d_stb_o                (D_STB_O),
   1.986 +    .d_we_o                 (D_WE_O),
   1.987 +    .d_cti_o                (D_CTI_O),
   1.988 +    .d_lock_o               (D_LOCK_O),
   1.989 +    .d_bte_o                (D_BTE_O)
   1.990 +    );      
   1.991 +       
   1.992 +// Adder       
   1.993 +lm32_adder adder (
   1.994 +    // ----- Inputs -------
   1.995 +    .adder_op_x             (adder_op_x),
   1.996 +    .adder_op_x_n           (adder_op_x_n),
   1.997 +    .operand_0_x            (operand_0_x),
   1.998 +    .operand_1_x            (operand_1_x),
   1.999 +    // ----- Outputs -------
  1.1000 +    .adder_result_x         (adder_result_x),
  1.1001 +    .adder_carry_n_x        (adder_carry_n_x),
  1.1002 +    .adder_overflow_x       (adder_overflow_x)
  1.1003 +    );
  1.1004 +
  1.1005 +// Logic operations
  1.1006 +lm32_logic_op logic_op (
  1.1007 +    // ----- Inputs -------
  1.1008 +    .logic_op_x             (logic_op_x),
  1.1009 +    .operand_0_x            (operand_0_x),
  1.1010 +
  1.1011 +    .operand_1_x            (operand_1_x),
  1.1012 +    // ----- Outputs -------
  1.1013 +    .logic_result_x         (logic_result_x)
  1.1014 +    );
  1.1015 +              
  1.1016 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.1017 +// Pipelined barrel-shifter
  1.1018 +lm32_shifter shifter (
  1.1019 +    // ----- Inputs -------
  1.1020 +    .clk_i                  (clk_i),
  1.1021 +    .rst_i                  (rst_i),
  1.1022 +    .stall_x                (stall_x),
  1.1023 +    .direction_x            (direction_x),
  1.1024 +    .sign_extend_x          (sign_extend_x),
  1.1025 +    .operand_0_x            (operand_0_x),
  1.1026 +    .operand_1_x            (operand_1_x),
  1.1027 +    // ----- Outputs -------
  1.1028 +    .shifter_result_m       (shifter_result_m)
  1.1029 +    );
  1.1030 +`endif
  1.1031 +
  1.1032 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.1033 +// Pipeline fixed-point multiplier
  1.1034 +lm32_multiplier multiplier (
  1.1035 +    // ----- Inputs -------
  1.1036 +    .clk_i                  (clk_i),
  1.1037 +    .rst_i                  (rst_i),
  1.1038 +    .stall_x                (stall_x),
  1.1039 +    .stall_m                (stall_m),
  1.1040 +    .operand_0              (d_result_0),
  1.1041 +    .operand_1              (d_result_1),
  1.1042 +    // ----- Outputs -------
  1.1043 +    .result                 (multiplier_result_w)    
  1.1044 +    );
  1.1045 +`endif
  1.1046 +
  1.1047 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  1.1048 +// Multi-cycle arithmetic
  1.1049 +lm32_mc_arithmetic mc_arithmetic (
  1.1050 +    // ----- Inputs -------
  1.1051 +    .clk_i                  (clk_i),
  1.1052 +    .rst_i                  (rst_i),
  1.1053 +    .stall_d                (stall_d),
  1.1054 +    .kill_x                 (kill_x),
  1.1055 +`ifdef CFG_MC_DIVIDE_ENABLED                  
  1.1056 +    .divide_d               (divide_q_d),
  1.1057 +    .modulus_d              (modulus_q_d),
  1.1058 +`endif
  1.1059 +`ifdef CFG_MC_MULTIPLY_ENABLED        
  1.1060 +    .multiply_d             (multiply_q_d),
  1.1061 +`endif
  1.1062 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  1.1063 +    .shift_left_d           (shift_left_q_d),
  1.1064 +    .shift_right_d          (shift_right_q_d),
  1.1065 +    .sign_extend_d          (sign_extend_d),
  1.1066 +`endif    
  1.1067 +    .operand_0_d            (d_result_0),
  1.1068 +    .operand_1_d            (d_result_1),
  1.1069 +    // ----- Outputs -------
  1.1070 +    .result_x               (mc_result_x),
  1.1071 +`ifdef CFG_MC_DIVIDE_ENABLED                  
  1.1072 +    .divide_by_zero_x       (divide_by_zero_x),
  1.1073 +`endif
  1.1074 +    .stall_request_x        (mc_stall_request_x)
  1.1075 +    );
  1.1076 +`endif
  1.1077 +              
  1.1078 +`ifdef CFG_INTERRUPTS_ENABLED
  1.1079 +// Interrupt unit
  1.1080 +lm32_interrupt interrupt (
  1.1081 +    // ----- Inputs -------
  1.1082 +    .clk_i                  (clk_i), 
  1.1083 +    .rst_i                  (rst_i),
  1.1084 +    // From external devices
  1.1085 +    .interrupt_n            (interrupt_n),
  1.1086 +    // From pipeline
  1.1087 +    .stall_x                (stall_x),
  1.1088 +`ifdef CFG_DEBUG_ENABLED
  1.1089 +    .non_debug_exception    (non_debug_exception_q_w), 
  1.1090 +    .debug_exception        (debug_exception_q_w),
  1.1091 +`else
  1.1092 +    .exception              (exception_q_w), 
  1.1093 +`endif
  1.1094 +    .eret_q_x               (eret_q_x),
  1.1095 +`ifdef CFG_DEBUG_ENABLED
  1.1096 +    .bret_q_x               (bret_q_x),
  1.1097 +`endif
  1.1098 +    .csr                    (csr_x),
  1.1099 +    .csr_write_data         (operand_1_x),
  1.1100 +    .csr_write_enable       (csr_write_enable_q_x),
  1.1101 +    // ----- Outputs -------
  1.1102 +    .interrupt_exception    (interrupt_exception),
  1.1103 +    // To pipeline
  1.1104 +    .csr_read_data          (interrupt_csr_read_data_x)
  1.1105 +    );
  1.1106 +`endif
  1.1107 +
  1.1108 +`ifdef CFG_JTAG_ENABLED
  1.1109 +// JTAG interface
  1.1110 +lm32_jtag jtag (
  1.1111 +    // ----- Inputs -------
  1.1112 +    .clk_i                  (clk_i),
  1.1113 +    .rst_i                  (rst_i),
  1.1114 +    // From JTAG
  1.1115 +    .jtag_clk               (jtag_clk),
  1.1116 +    .jtag_update            (jtag_update),
  1.1117 +    .jtag_reg_q             (jtag_reg_q),
  1.1118 +    .jtag_reg_addr_q        (jtag_reg_addr_q),
  1.1119 +    // From pipeline
  1.1120 +`ifdef CFG_JTAG_UART_ENABLED
  1.1121 +    .csr                    (csr_x),
  1.1122 +    .csr_write_data         (operand_1_x),
  1.1123 +    .csr_write_enable       (csr_write_enable_q_x),
  1.1124 +    .stall_x                (stall_x),
  1.1125 +`endif
  1.1126 +`ifdef CFG_HW_DEBUG_ENABLED
  1.1127 +    .jtag_read_data         (jtag_read_data),
  1.1128 +    .jtag_access_complete   (jtag_access_complete),
  1.1129 +`endif
  1.1130 +`ifdef CFG_DEBUG_ENABLED
  1.1131 +    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
  1.1132 +`endif    
  1.1133 +    // ----- Outputs -------
  1.1134 +    // To pipeline
  1.1135 +`ifdef CFG_JTAG_UART_ENABLED
  1.1136 +    .jtx_csr_read_data      (jtx_csr_read_data),
  1.1137 +    .jrx_csr_read_data      (jrx_csr_read_data),
  1.1138 +`endif
  1.1139 +`ifdef CFG_HW_DEBUG_ENABLED
  1.1140 +    .jtag_csr_write_enable  (jtag_csr_write_enable),
  1.1141 +    .jtag_csr_write_data    (jtag_csr_write_data),
  1.1142 +    .jtag_csr               (jtag_csr),
  1.1143 +    .jtag_read_enable       (jtag_read_enable),
  1.1144 +    .jtag_write_enable      (jtag_write_enable),
  1.1145 +    .jtag_write_data        (jtag_write_data),
  1.1146 +    .jtag_address           (jtag_address),
  1.1147 +`endif
  1.1148 +`ifdef CFG_DEBUG_ENABLED
  1.1149 +    .jtag_break             (jtag_break),
  1.1150 +    .jtag_reset             (reset_exception),
  1.1151 +`endif
  1.1152 +    // To JTAG 
  1.1153 +    .jtag_reg_d             (jtag_reg_d),
  1.1154 +    .jtag_reg_addr_d        (jtag_reg_addr_d)
  1.1155 +    );
  1.1156 +`endif
  1.1157 +
  1.1158 +`ifdef CFG_DEBUG_ENABLED
  1.1159 +// Debug unit
  1.1160 +lm32_debug #(
  1.1161 +    .breakpoints            (breakpoints),
  1.1162 +    .watchpoints            (watchpoints)
  1.1163 +  ) hw_debug (
  1.1164 +    // ----- Inputs -------
  1.1165 +    .clk_i                  (clk_i), 
  1.1166 +    .rst_i                  (rst_i),
  1.1167 +    .pc_x                   (pc_x),
  1.1168 +    .load_x                 (load_x),
  1.1169 +    .store_x                (store_x),
  1.1170 +    .load_store_address_x   (adder_result_x),
  1.1171 +    .csr_write_enable_x     (csr_write_enable_q_x),
  1.1172 +    .csr_write_data         (operand_1_x),
  1.1173 +    .csr_x                  (csr_x),
  1.1174 +`ifdef CFG_HW_DEBUG_ENABLED
  1.1175 +    .jtag_csr_write_enable  (jtag_csr_write_enable),
  1.1176 +    .jtag_csr_write_data    (jtag_csr_write_data),
  1.1177 +    .jtag_csr               (jtag_csr),
  1.1178 +`endif
  1.1179 +`ifdef LM32_SINGLE_STEP_ENABLED
  1.1180 +    .eret_q_x               (eret_q_x),
  1.1181 +    .bret_q_x               (bret_q_x),
  1.1182 +    .stall_x                (stall_x),
  1.1183 +    .exception_x            (exception_x),
  1.1184 +    .q_x                    (q_x),
  1.1185 +`ifdef CFG_DCACHE_ENABLED
  1.1186 +    .dcache_refill_request  (dcache_refill_request),
  1.1187 +`endif
  1.1188 +`endif
  1.1189 +    // ----- Outputs -------
  1.1190 +`ifdef LM32_SINGLE_STEP_ENABLED
  1.1191 +    .dc_ss                  (dc_ss),
  1.1192 +`endif
  1.1193 +    .dc_re                  (dc_re),
  1.1194 +    .bp_match               (bp_match),
  1.1195 +    .wp_match               (wp_match)
  1.1196 +    );
  1.1197 +`endif
  1.1198 +
  1.1199 +// Register file
  1.1200 +
  1.1201 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  1.1202 +   /*----------------------------------------------------------------------
  1.1203 +    Register File is implemented using EBRs. There can be three accesses to
  1.1204 +    the register file in each cycle: two reads and one write. On-chip block
  1.1205 +    RAM has two read/write ports. To accomodate three accesses, two on-chip
  1.1206 +    block RAMs are used (each register file "write" is made to both block
  1.1207 +    RAMs).
  1.1208 +    
  1.1209 +    One limitation of the on-chip block RAMs is that one cannot perform a 
  1.1210 +    read and write to same location in a cycle (if this is done, then the
  1.1211 +    data read out is indeterminate).
  1.1212 +    ----------------------------------------------------------------------*/
  1.1213 +   wire [31:0] regfile_data_0, regfile_data_1;
  1.1214 +   reg [31:0]  w_result_d;
  1.1215 +   reg 	       regfile_raw_0, regfile_raw_0_nxt;
  1.1216 +   reg 	       regfile_raw_1, regfile_raw_1_nxt;
  1.1217 +   
  1.1218 +   /*----------------------------------------------------------------------
  1.1219 +    Check if read and write is being performed to same register in current 
  1.1220 +    cycle? This is done by comparing the read and write IDXs.
  1.1221 +    ----------------------------------------------------------------------*/
  1.1222 +   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
  1.1223 +     begin
  1.1224 +	if (reg_write_enable_q_w
  1.1225 +	    && (write_idx_w == instruction_f[25:21]))
  1.1226 +	  regfile_raw_0_nxt = 1'b1;
  1.1227 +	else
  1.1228 +	  regfile_raw_0_nxt = 1'b0;
  1.1229 +	
  1.1230 +	if (reg_write_enable_q_w
  1.1231 +	    && (write_idx_w == instruction_f[20:16]))
  1.1232 +	  regfile_raw_1_nxt = 1'b1;
  1.1233 +	else
  1.1234 +	  regfile_raw_1_nxt = 1'b0;
  1.1235 +     end
  1.1236 +   
  1.1237 +   /*----------------------------------------------------------------------
  1.1238 +    Select latched (delayed) write value or data from register file. If 
  1.1239 +    read in previous cycle was performed to register written to in same
  1.1240 +    cycle, then latched (delayed) write value is selected.
  1.1241 +    ----------------------------------------------------------------------*/
  1.1242 +   always @(regfile_raw_0 or w_result_d or regfile_data_0)
  1.1243 +     if (regfile_raw_0)
  1.1244 +       reg_data_live_0 = w_result_d;
  1.1245 +     else
  1.1246 +       reg_data_live_0 = regfile_data_0;
  1.1247 +   
  1.1248 +   /*----------------------------------------------------------------------
  1.1249 +    Select latched (delayed) write value or data from register file. If 
  1.1250 +    read in previous cycle was performed to register written to in same
  1.1251 +    cycle, then latched (delayed) write value is selected.
  1.1252 +    ----------------------------------------------------------------------*/
  1.1253 +   always @(regfile_raw_1 or w_result_d or regfile_data_1)
  1.1254 +     if (regfile_raw_1)
  1.1255 +       reg_data_live_1 = w_result_d;
  1.1256 +     else
  1.1257 +       reg_data_live_1 = regfile_data_1;
  1.1258 +   
  1.1259 +   /*----------------------------------------------------------------------
  1.1260 +    Latch value written to register file
  1.1261 +    ----------------------------------------------------------------------*/
  1.1262 +   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.1263 +     if (rst_i == `TRUE)
  1.1264 +       begin
  1.1265 +	  regfile_raw_0 <= 1'b0;
  1.1266 +	  regfile_raw_1 <= 1'b0;
  1.1267 +	  w_result_d <= 32'b0;
  1.1268 +       end
  1.1269 +     else
  1.1270 +       begin
  1.1271 +	  regfile_raw_0 <= regfile_raw_0_nxt;
  1.1272 +	  regfile_raw_1 <= regfile_raw_1_nxt;
  1.1273 +	  w_result_d <= w_result;
  1.1274 +       end
  1.1275 +   
  1.1276 +   /*----------------------------------------------------------------------
  1.1277 +    Register file instantiation as Pseudo-Dual Port EBRs.
  1.1278 +    ----------------------------------------------------------------------*/
  1.1279 +   pmi_ram_dp
  1.1280 +     #(
  1.1281 +       // ----- Parameters -----
  1.1282 +       .pmi_wr_addr_depth(1<<5),
  1.1283 +       .pmi_wr_addr_width(5),
  1.1284 +       .pmi_wr_data_width(32),
  1.1285 +       .pmi_rd_addr_depth(1<<5),
  1.1286 +       .pmi_rd_addr_width(5),
  1.1287 +       .pmi_rd_data_width(32),
  1.1288 +       .pmi_regmode("noreg"),
  1.1289 +       .pmi_gsr("enable"),
  1.1290 +       .pmi_resetmode("sync"),
  1.1291 +       .pmi_init_file("none"),
  1.1292 +       .pmi_init_file_format("binary"),
  1.1293 +       .pmi_family(`LATTICE_FAMILY),
  1.1294 +       .module_type("pmi_ram_dp")
  1.1295 +       )
  1.1296 +   reg_0
  1.1297 +     (
  1.1298 +      // ----- Inputs -----
  1.1299 +      .Data(w_result),
  1.1300 +      .WrAddress(write_idx_w),
  1.1301 +      .RdAddress(instruction_f[25:21]),
  1.1302 +      .WrClock(clk_i),
  1.1303 +      .RdClock(clk_i),
  1.1304 +      .WrClockEn(`TRUE),
  1.1305 +      .RdClockEn(`TRUE),
  1.1306 +      .WE(reg_write_enable_q_w),
  1.1307 +      .Reset(rst_i), 
  1.1308 +      // ----- Outputs -----
  1.1309 +      .Q(regfile_data_0)
  1.1310 +      );
  1.1311 +
  1.1312 +   pmi_ram_dp
  1.1313 +     #(
  1.1314 +       // ----- Parameters -----
  1.1315 +       .pmi_wr_addr_depth(1<<5),
  1.1316 +       .pmi_wr_addr_width(5),
  1.1317 +       .pmi_wr_data_width(32),
  1.1318 +       .pmi_rd_addr_depth(1<<5),
  1.1319 +       .pmi_rd_addr_width(5),
  1.1320 +       .pmi_rd_data_width(32),
  1.1321 +       .pmi_regmode("noreg"),
  1.1322 +       .pmi_gsr("enable"),
  1.1323 +       .pmi_resetmode("sync"),
  1.1324 +       .pmi_init_file("none"),
  1.1325 +       .pmi_init_file_format("binary"),
  1.1326 +       .pmi_family(`LATTICE_FAMILY),
  1.1327 +       .module_type("pmi_ram_dp")
  1.1328 +       )
  1.1329 +   reg_1
  1.1330 +     (
  1.1331 +      // ----- Inputs -----
  1.1332 +      .Data(w_result),
  1.1333 +      .WrAddress(write_idx_w),
  1.1334 +      .RdAddress(instruction_f[20:16]),
  1.1335 +      .WrClock(clk_i),
  1.1336 +      .RdClock(clk_i),
  1.1337 +      .WrClockEn(`TRUE),
  1.1338 +      .RdClockEn(`TRUE),
  1.1339 +      .WE(reg_write_enable_q_w),
  1.1340 +      .Reset(rst_i), 
  1.1341 +      // ----- Outputs -----
  1.1342 +      .Q(regfile_data_1)
  1.1343 +      );
  1.1344 +`endif
  1.1345 +
  1.1346 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  1.1347 +   pmi_ram_dp
  1.1348 +     #(
  1.1349 +       // ----- Parameters -----
  1.1350 +       .pmi_wr_addr_depth(1<<5),
  1.1351 +       .pmi_wr_addr_width(5),
  1.1352 +       .pmi_wr_data_width(32),
  1.1353 +       .pmi_rd_addr_depth(1<<5),
  1.1354 +       .pmi_rd_addr_width(5),
  1.1355 +       .pmi_rd_data_width(32),
  1.1356 +       .pmi_regmode("noreg"),
  1.1357 +       .pmi_gsr("enable"),
  1.1358 +       .pmi_resetmode("sync"),
  1.1359 +       .pmi_init_file("none"),
  1.1360 +       .pmi_init_file_format("binary"),
  1.1361 +       .pmi_family(`LATTICE_FAMILY),
  1.1362 +       .module_type("pmi_ram_dp")
  1.1363 +       )
  1.1364 +   reg_0
  1.1365 +     (
  1.1366 +      // ----- Inputs -----
  1.1367 +      .Data(w_result),
  1.1368 +      .WrAddress(write_idx_w),
  1.1369 +      .RdAddress(read_idx_0_d),
  1.1370 +      .WrClock(clk_i),
  1.1371 +      .RdClock(clk_n_i),
  1.1372 +      .WrClockEn(`TRUE),
  1.1373 +      .RdClockEn(stall_f == `FALSE),
  1.1374 +      .WE(reg_write_enable_q_w),
  1.1375 +      .Reset(rst_i), 
  1.1376 +      // ----- Outputs -----
  1.1377 +      .Q(reg_data_0)
  1.1378 +      );
  1.1379 +   
  1.1380 +   pmi_ram_dp
  1.1381 +     #(
  1.1382 +       // ----- Parameters -----
  1.1383 +       .pmi_wr_addr_depth(1<<5),
  1.1384 +       .pmi_wr_addr_width(5),
  1.1385 +       .pmi_wr_data_width(32),
  1.1386 +       .pmi_rd_addr_depth(1<<5),
  1.1387 +       .pmi_rd_addr_width(5),
  1.1388 +       .pmi_rd_data_width(32),
  1.1389 +       .pmi_regmode("noreg"),
  1.1390 +       .pmi_gsr("enable"),
  1.1391 +       .pmi_resetmode("sync"),
  1.1392 +       .pmi_init_file("none"),
  1.1393 +       .pmi_init_file_format("binary"),
  1.1394 +       .pmi_family(`LATTICE_FAMILY),
  1.1395 +       .module_type("pmi_ram_dp")
  1.1396 +       )
  1.1397 +   reg_1
  1.1398 +     (
  1.1399 +      // ----- Inputs -----
  1.1400 +      .Data(w_result),
  1.1401 +      .WrAddress(write_idx_w),
  1.1402 +      .RdAddress(read_idx_1_d),
  1.1403 +      .WrClock(clk_i),
  1.1404 +      .RdClock(clk_n_i),
  1.1405 +      .WrClockEn(`TRUE),
  1.1406 +      .RdClockEn(stall_f == `FALSE),
  1.1407 +      .WE(reg_write_enable_q_w),
  1.1408 +      .Reset(rst_i), 
  1.1409 +      // ----- Outputs -----
  1.1410 +      .Q(reg_data_1)
  1.1411 +      );
  1.1412 +`endif
  1.1413 +
  1.1414 +
  1.1415 +/////////////////////////////////////////////////////
  1.1416 +// Combinational Logic
  1.1417 +/////////////////////////////////////////////////////
  1.1418 +
  1.1419 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  1.1420 +// Select between buffered and live data from register file
  1.1421 +assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
  1.1422 +assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
  1.1423 +`endif
  1.1424 +`ifdef LM32_EBR_REGISTER_FILE
  1.1425 +`else
  1.1426 +// Register file read ports
  1.1427 +assign reg_data_0 = registers[read_idx_0_d];
  1.1428 +assign reg_data_1 = registers[read_idx_1_d];
  1.1429 +`endif
  1.1430 +
  1.1431 +// Detect read-after-write hazzards
  1.1432 +assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
  1.1433 +assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
  1.1434 +assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
  1.1435 +assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
  1.1436 +assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
  1.1437 +assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
  1.1438 +
  1.1439 +// Interlock detection - Raise an interlock for RAW hazzards 
  1.1440 +always @(*)
  1.1441 +begin
  1.1442 +    if (   (   (x_bypass_enable_x == `FALSE)
  1.1443 +            && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
  1.1444 +                || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
  1.1445 +               )
  1.1446 +           )
  1.1447 +        || (   (m_bypass_enable_m == `FALSE)
  1.1448 +            && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
  1.1449 +                || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
  1.1450 +               )
  1.1451 +           )
  1.1452 +       )
  1.1453 +        interlock = `TRUE;
  1.1454 +    else
  1.1455 +        interlock = `FALSE;
  1.1456 +end
  1.1457 +
  1.1458 +// Bypass for reg port 0
  1.1459 +always @(*)
  1.1460 +begin
  1.1461 +    if (raw_x_0 == `TRUE)        
  1.1462 +        bypass_data_0 = x_result;
  1.1463 +    else if (raw_m_0 == `TRUE)
  1.1464 +        bypass_data_0 = m_result;
  1.1465 +    else if (raw_w_0 == `TRUE)
  1.1466 +        bypass_data_0 = w_result;
  1.1467 +    else
  1.1468 +        bypass_data_0 = reg_data_0;
  1.1469 +end
  1.1470 +
  1.1471 +// Bypass for reg port 1
  1.1472 +always @(*)
  1.1473 +begin
  1.1474 +    if (raw_x_1 == `TRUE)
  1.1475 +        bypass_data_1 = x_result;
  1.1476 +    else if (raw_m_1 == `TRUE)
  1.1477 +        bypass_data_1 = m_result;
  1.1478 +    else if (raw_w_1 == `TRUE)
  1.1479 +        bypass_data_1 = w_result;
  1.1480 +    else
  1.1481 +        bypass_data_1 = reg_data_1;
  1.1482 +end
  1.1483 +
  1.1484 +   /*----------------------------------------------------------------------
  1.1485 +    Branch prediction is performed in D stage of pipeline. Only PC-relative
  1.1486 +    branches are predicted: forward-pointing conditional branches are not-
  1.1487 +    taken, while backward-pointing conditional branches are taken. 
  1.1488 +    Unconditional branches are always predicted taken!
  1.1489 +    ----------------------------------------------------------------------*/
  1.1490 +   assign branch_predict_d = bi_unconditional | bi_conditional;
  1.1491 +   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
  1.1492 +   
  1.1493 +   // Compute branch target address: Branch PC PLUS Offset
  1.1494 +   assign branch_target_d = pc_d + branch_offset_d;
  1.1495 +
  1.1496 +   // Compute fetch address. Address of instruction sequentially after the
  1.1497 +   // branch if branch is not taken. Target address of branch is branch is
  1.1498 +   // taken
  1.1499 +   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
  1.1500 +
  1.1501 +// D stage result selection
  1.1502 +always @(*)
  1.1503 +begin
  1.1504 +    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
  1.1505 +    case (d_result_sel_1_d)
  1.1506 +    `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
  1.1507 +    `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
  1.1508 +    `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
  1.1509 +    default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
  1.1510 +    endcase
  1.1511 +end
  1.1512 +
  1.1513 +`ifdef CFG_USER_ENABLED    
  1.1514 +// Operands for user-defined instructions
  1.1515 +assign user_operand_0 = operand_0_x;
  1.1516 +assign user_operand_1 = operand_1_x;
  1.1517 +`endif
  1.1518 +
  1.1519 +`ifdef CFG_SIGN_EXTEND_ENABLED
  1.1520 +// Sign-extension
  1.1521 +assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
  1.1522 +assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
  1.1523 +assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
  1.1524 +`endif
  1.1525 +
  1.1526 +`ifdef LM32_NO_BARREL_SHIFT
  1.1527 +// Only single bit shift operations are supported when barrel-shifter isn't implemented
  1.1528 +assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
  1.1529 +`endif
  1.1530 +
  1.1531 +// Condition evaluation
  1.1532 +assign cmp_zero = operand_0_x == operand_1_x;
  1.1533 +assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
  1.1534 +assign cmp_overflow = adder_overflow_x;
  1.1535 +assign cmp_carry_n = adder_carry_n_x;
  1.1536 +always @(*)
  1.1537 +begin
  1.1538 +    case (condition_x)
  1.1539 +    `LM32_CONDITION_U1:   condition_met_x = `TRUE;
  1.1540 +    `LM32_CONDITION_U2:   condition_met_x = `TRUE;
  1.1541 +    `LM32_CONDITION_E:    condition_met_x = cmp_zero;
  1.1542 +    `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
  1.1543 +    `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
  1.1544 +    `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
  1.1545 +    `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
  1.1546 +    `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
  1.1547 +    default:              condition_met_x = 1'bx;
  1.1548 +    endcase 
  1.1549 +end
  1.1550 +
  1.1551 +// X stage result selection
  1.1552 +always @(*)
  1.1553 +begin
  1.1554 +    x_result =   x_result_sel_add_x ? adder_result_x 
  1.1555 +               : x_result_sel_csr_x ? csr_read_data_x
  1.1556 +`ifdef CFG_SIGN_EXTEND_ENABLED
  1.1557 +               : x_result_sel_sext_x ? sext_result_x
  1.1558 +`endif
  1.1559 +`ifdef CFG_USER_ENABLED
  1.1560 +               : x_result_sel_user_x ? user_result
  1.1561 +`endif
  1.1562 +`ifdef LM32_NO_BARREL_SHIFT
  1.1563 +               : x_result_sel_shift_x ? shifter_result_x
  1.1564 +`endif
  1.1565 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  1.1566 +               : x_result_sel_mc_arith_x ? mc_result_x
  1.1567 +`endif
  1.1568 +               : logic_result_x;
  1.1569 +end
  1.1570 +
  1.1571 +// M stage result selection
  1.1572 +always @(*)
  1.1573 +begin
  1.1574 +    m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
  1.1575 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.1576 +               : m_result_sel_shift_m ? shifter_result_m
  1.1577 +`endif
  1.1578 +               : operand_m; 
  1.1579 +end
  1.1580 +
  1.1581 +// W stage result selection
  1.1582 +always @(*)
  1.1583 +begin
  1.1584 +    w_result =    w_result_sel_load_w ? load_data_w
  1.1585 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.1586 +                : w_result_sel_mul_w ? multiplier_result_w
  1.1587 +`endif
  1.1588 +                : operand_w;
  1.1589 +end
  1.1590 +
  1.1591 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1.1592 +// Indicate when a branch should be taken in X stage
  1.1593 +assign branch_taken_x =      (stall_x == `FALSE)
  1.1594 +                          && (   (branch_x == `TRUE)
  1.1595 +                              && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
  1.1596 +                              && (valid_x == `TRUE)
  1.1597 +                              && (branch_predict_x == `FALSE)
  1.1598 +                             ); 
  1.1599 +`endif
  1.1600 +
  1.1601 +// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
  1.1602 +assign branch_taken_m =      (stall_m == `FALSE) 
  1.1603 +                          && (   (   (branch_m == `TRUE) 
  1.1604 +                                  && (valid_m == `TRUE)
  1.1605 +                                  && (   (   (condition_met_m == `TRUE)
  1.1606 +					  && (branch_predict_taken_m == `FALSE)
  1.1607 +					 )
  1.1608 +				      || (   (condition_met_m == `FALSE)
  1.1609 +					  && (branch_predict_m == `TRUE)
  1.1610 +					  && (branch_predict_taken_m == `TRUE)
  1.1611 +					 )
  1.1612 +				     )
  1.1613 +                                 ) 
  1.1614 +                              || (exception_m == `TRUE)
  1.1615 +                             );
  1.1616 +
  1.1617 +// Indicate when a branch in M stage is mispredicted as being taken
  1.1618 +assign branch_mispredict_taken_m =    (condition_met_m == `FALSE)
  1.1619 +                                   && (branch_predict_m == `TRUE)
  1.1620 +	   			   && (branch_predict_taken_m == `TRUE);
  1.1621 +   
  1.1622 +// Indicate when a branch in M stage will cause flush in X stage
  1.1623 +assign branch_flushX_m =    (stall_m == `FALSE)
  1.1624 +                         && (   (   (branch_m == `TRUE) 
  1.1625 +                                 && (valid_m == `TRUE)
  1.1626 +			         && (   (condition_met_m == `TRUE)
  1.1627 +				     || (   (condition_met_m == `FALSE)
  1.1628 +					 && (branch_predict_m == `TRUE)
  1.1629 +					 && (branch_predict_taken_m == `TRUE)
  1.1630 +					)
  1.1631 +				    )
  1.1632 +			        )
  1.1633 +			     || (exception_m == `TRUE)
  1.1634 +			    );
  1.1635 +
  1.1636 +// Generate signal that will kill instructions in each pipeline stage when necessary
  1.1637 +assign kill_f =    (   (valid_d == `TRUE)
  1.1638 +                    && (branch_predict_taken_d == `TRUE)
  1.1639 +		   )
  1.1640 +                || (branch_taken_m == `TRUE) 
  1.1641 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1.1642 +                || (branch_taken_x == `TRUE)
  1.1643 +`endif
  1.1644 +`ifdef CFG_ICACHE_ENABLED
  1.1645 +                || (icache_refill_request == `TRUE) 
  1.1646 +`endif
  1.1647 +`ifdef CFG_DCACHE_ENABLED                
  1.1648 +                || (dcache_refill_request == `TRUE)
  1.1649 +`endif
  1.1650 +                ;
  1.1651 +assign kill_d =    (branch_taken_m == `TRUE) 
  1.1652 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1.1653 +                || (branch_taken_x == `TRUE)
  1.1654 +`endif
  1.1655 +`ifdef CFG_ICACHE_ENABLED
  1.1656 +                || (icache_refill_request == `TRUE)     
  1.1657 +`endif                
  1.1658 +`ifdef CFG_DCACHE_ENABLED                
  1.1659 +                || (dcache_refill_request == `TRUE)
  1.1660 +`endif
  1.1661 +                ;
  1.1662 +assign kill_x =    (branch_flushX_m == `TRUE) 
  1.1663 +`ifdef CFG_DCACHE_ENABLED                
  1.1664 +                || (dcache_refill_request == `TRUE)
  1.1665 +`endif
  1.1666 +                ;
  1.1667 +assign kill_m =    `FALSE
  1.1668 +`ifdef CFG_DCACHE_ENABLED                
  1.1669 +                || (dcache_refill_request == `TRUE)
  1.1670 +`endif
  1.1671 +                ;                
  1.1672 +assign kill_w =    `FALSE
  1.1673 +`ifdef CFG_DCACHE_ENABLED                
  1.1674 +                || (dcache_refill_request == `TRUE)
  1.1675 +`endif                
  1.1676 +                ;
  1.1677 +
  1.1678 +// Exceptions
  1.1679 +
  1.1680 +`ifdef CFG_DEBUG_ENABLED
  1.1681 +assign breakpoint_exception =    (   (   (break_x == `TRUE)
  1.1682 +				      || (bp_match == `TRUE)
  1.1683 +				     )
  1.1684 +				  && (valid_x == `TRUE)
  1.1685 +				 )
  1.1686 +`ifdef CFG_JTAG_ENABLED
  1.1687 +                              || (jtag_break == `TRUE)
  1.1688 +`endif
  1.1689 +                              ;
  1.1690 +`endif
  1.1691 +
  1.1692 +`ifdef CFG_DEBUG_ENABLED
  1.1693 +assign watchpoint_exception = wp_match == `TRUE;
  1.1694 +`endif
  1.1695 +
  1.1696 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.1697 +assign instruction_bus_error_exception = (   (bus_error_x == `TRUE)
  1.1698 +                                          && (valid_x == `TRUE)
  1.1699 +                                         );
  1.1700 +assign data_bus_error_exception = data_bus_error_seen == `TRUE;
  1.1701 +`endif
  1.1702 +
  1.1703 +`ifdef CFG_MC_DIVIDE_ENABLED
  1.1704 +assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
  1.1705 +`endif
  1.1706 +
  1.1707 +assign system_call_exception = (   (scall_x == `TRUE)
  1.1708 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.1709 +                                && (valid_x == `TRUE)
  1.1710 +`endif
  1.1711 +			       );
  1.1712 +
  1.1713 +`ifdef CFG_DEBUG_ENABLED
  1.1714 +assign debug_exception_x =  (breakpoint_exception == `TRUE)
  1.1715 +                         || (watchpoint_exception == `TRUE)
  1.1716 +                         ;
  1.1717 +
  1.1718 +assign non_debug_exception_x = (system_call_exception == `TRUE)
  1.1719 +`ifdef CFG_JTAG_ENABLED
  1.1720 +                            || (reset_exception == `TRUE)
  1.1721 +`endif
  1.1722 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.1723 +                            || (instruction_bus_error_exception == `TRUE)
  1.1724 +                            || (data_bus_error_exception == `TRUE)
  1.1725 +`endif
  1.1726 +`ifdef CFG_MC_DIVIDE_ENABLED
  1.1727 +                            || (divide_by_zero_exception == `TRUE)
  1.1728 +`endif
  1.1729 +`ifdef CFG_INTERRUPTS_ENABLED
  1.1730 +                            || (   (interrupt_exception == `TRUE)
  1.1731 +`ifdef LM32_SINGLE_STEP_ENABLED
  1.1732 +                                && (dc_ss == `FALSE)
  1.1733 +`endif                            
  1.1734 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.1735 + 				&& (store_q_m == `FALSE)
  1.1736 +				&& (D_CYC_O == `FALSE)
  1.1737 +`endif
  1.1738 +                               )
  1.1739 +`endif
  1.1740 +                            ;
  1.1741 +
  1.1742 +assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
  1.1743 +`else
  1.1744 +assign exception_x =           (system_call_exception == `TRUE)
  1.1745 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.1746 +                            || (instruction_bus_error_exception == `TRUE)
  1.1747 +                            || (data_bus_error_exception == `TRUE)
  1.1748 +`endif
  1.1749 +`ifdef CFG_MC_DIVIDE_ENABLED
  1.1750 +                            || (divide_by_zero_exception == `TRUE)
  1.1751 +`endif
  1.1752 +`ifdef CFG_INTERRUPTS_ENABLED
  1.1753 +                            || (   (interrupt_exception == `TRUE)
  1.1754 +`ifdef LM32_SINGLE_STEP_ENABLED
  1.1755 +                                && (dc_ss == `FALSE)
  1.1756 +`endif                            
  1.1757 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.1758 + 				&& (store_q_m == `FALSE)
  1.1759 +				&& (D_CYC_O == `FALSE)
  1.1760 +`endif
  1.1761 +                               )
  1.1762 +`endif
  1.1763 +                            ;
  1.1764 +`endif
  1.1765 +
  1.1766 +// Exception ID
  1.1767 +always @(*)
  1.1768 +begin
  1.1769 +`ifdef CFG_DEBUG_ENABLED
  1.1770 +`ifdef CFG_JTAG_ENABLED
  1.1771 +    if (reset_exception == `TRUE)
  1.1772 +        eid_x = `LM32_EID_RESET;
  1.1773 +    else
  1.1774 +`endif     
  1.1775 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.1776 +         if (data_bus_error_exception == `TRUE)
  1.1777 +        eid_x = `LM32_EID_DATA_BUS_ERROR;
  1.1778 +    else
  1.1779 +`endif
  1.1780 +         if (breakpoint_exception == `TRUE)
  1.1781 +        eid_x = `LM32_EID_BREAKPOINT;
  1.1782 +    else
  1.1783 +`endif
  1.1784 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.1785 +         if (data_bus_error_exception == `TRUE)
  1.1786 +        eid_x = `LM32_EID_DATA_BUS_ERROR;
  1.1787 +    else
  1.1788 +         if (instruction_bus_error_exception == `TRUE)
  1.1789 +        eid_x = `LM32_EID_INST_BUS_ERROR;
  1.1790 +    else
  1.1791 +`endif
  1.1792 +`ifdef CFG_DEBUG_ENABLED
  1.1793 +         if (watchpoint_exception == `TRUE)
  1.1794 +        eid_x = `LM32_EID_WATCHPOINT;
  1.1795 +    else 
  1.1796 +`endif
  1.1797 +`ifdef CFG_MC_DIVIDE_ENABLED
  1.1798 +         if (divide_by_zero_exception == `TRUE)
  1.1799 +        eid_x = `LM32_EID_DIVIDE_BY_ZERO;
  1.1800 +    else
  1.1801 +`endif
  1.1802 +`ifdef CFG_INTERRUPTS_ENABLED
  1.1803 +         if (   (interrupt_exception == `TRUE)
  1.1804 +`ifdef LM32_SINGLE_STEP_ENABLED
  1.1805 +             && (dc_ss == `FALSE)
  1.1806 +`endif                            
  1.1807 +            )
  1.1808 +        eid_x = `LM32_EID_INTERRUPT;
  1.1809 +    else
  1.1810 +`endif
  1.1811 +        eid_x = `LM32_EID_SCALL;
  1.1812 +end
  1.1813 +
  1.1814 +// Stall generation
  1.1815 +
  1.1816 +assign stall_a = (stall_f == `TRUE);
  1.1817 +                
  1.1818 +assign stall_f = (stall_d == `TRUE);
  1.1819 +                
  1.1820 +assign stall_d =   (stall_x == `TRUE) 
  1.1821 +                || (   (interlock == `TRUE)
  1.1822 +                    && (kill_d == `FALSE)
  1.1823 +                   ) 
  1.1824 +		|| (   (   (eret_d == `TRUE)
  1.1825 +			|| (scall_d == `TRUE)
  1.1826 +			|| (bus_error_d == `TRUE)
  1.1827 +		       )
  1.1828 +		    && (   (load_q_x == `TRUE)
  1.1829 +			|| (load_q_m == `TRUE)
  1.1830 +			|| (store_q_x == `TRUE)
  1.1831 +			|| (store_q_m == `TRUE)
  1.1832 +			|| (D_CYC_O == `TRUE)
  1.1833 +		       )
  1.1834 +                    && (kill_d == `FALSE)
  1.1835 +		   )
  1.1836 +`ifdef CFG_DEBUG_ENABLED
  1.1837 +		|| (   (   (break_d == `TRUE)
  1.1838 +			|| (bret_d == `TRUE)
  1.1839 +		       )
  1.1840 +		    && (   (load_q_x == `TRUE)
  1.1841 +			|| (store_q_x == `TRUE)
  1.1842 +			|| (load_q_m == `TRUE)
  1.1843 +			|| (store_q_m == `TRUE)
  1.1844 +			|| (D_CYC_O == `TRUE)
  1.1845 +		       )
  1.1846 +                    && (kill_d == `FALSE)
  1.1847 +		   )
  1.1848 +`endif                   
  1.1849 +                || (   (csr_write_enable_d == `TRUE)
  1.1850 +                    && (load_q_x == `TRUE)
  1.1851 +                   )                      
  1.1852 +                ;
  1.1853 +                
  1.1854 +assign stall_x =    (stall_m == `TRUE)
  1.1855 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  1.1856 +                 || (   (mc_stall_request_x == `TRUE)
  1.1857 +                     && (kill_x == `FALSE)
  1.1858 +                    ) 
  1.1859 +`endif
  1.1860 +`ifdef CFG_IROM_ENABLED
  1.1861 +                 // Stall load/store instruction in D stage if there is an ongoing store
  1.1862 +                 // operation to instruction ROM in M stage
  1.1863 +                 || (   (irom_stall_request_x == `TRUE)
  1.1864 +		     && (   (load_d == `TRUE)
  1.1865 +			 || (store_d == `TRUE)
  1.1866 +			)
  1.1867 +		    )
  1.1868 +`endif
  1.1869 +                 ;
  1.1870 +
  1.1871 +assign stall_m =    (stall_wb_load == `TRUE)
  1.1872 +`ifdef CFG_SIZE_OVER_SPEED
  1.1873 +                 || (D_CYC_O == `TRUE)
  1.1874 +`else
  1.1875 +                 || (   (D_CYC_O == `TRUE)
  1.1876 +                     && (   (store_m == `TRUE)
  1.1877 +		         /*
  1.1878 +			  Bug: Following loop does not allow interrupts to be services since
  1.1879 +			  either D_CYC_O or store_m is always high during entire duration of
  1.1880 +			  loop.
  1.1881 +		          L1:	addi	r1, r1, 1
  1.1882 +			  	sw	(r2,0), r1
  1.1883 +			  	bi	L1
  1.1884 +			  
  1.1885 +			  Introduce a single-cycle stall when a wishbone cycle is in progress
  1.1886 +			  and a new store instruction is in Execute stage and a interrupt
  1.1887 +			  exception has occured. This stall will ensure that D_CYC_O and 
  1.1888 +			  store_m will both be low for one cycle.
  1.1889 +			  */
  1.1890 +		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
  1.1891 +                         || (load_m == `TRUE)
  1.1892 +                         || (load_x == `TRUE)
  1.1893 +                        ) 
  1.1894 +                    ) 
  1.1895 +`endif                 
  1.1896 +`ifdef CFG_DCACHE_ENABLED
  1.1897 +                 || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
  1.1898 +`endif                                    
  1.1899 +`ifdef CFG_ICACHE_ENABLED
  1.1900 +                 || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
  1.1901 +                 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 
  1.1902 +`else
  1.1903 +`ifdef CFG_IWB_ENABLED
  1.1904 +                 || (I_CYC_O == `TRUE)            
  1.1905 +`endif
  1.1906 +`endif                               
  1.1907 +`ifdef CFG_USER_ENABLED
  1.1908 +                 || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
  1.1909 +                     && (user_complete == `FALSE)
  1.1910 +                    )
  1.1911 +`endif
  1.1912 +                 ;      
  1.1913 +
  1.1914 +// Qualify state changing control signals
  1.1915 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  1.1916 +assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
  1.1917 +`endif
  1.1918 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  1.1919 +assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
  1.1920 +assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
  1.1921 +`endif
  1.1922 +`ifdef CFG_MC_MULTIPLY_ENABLED
  1.1923 +assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
  1.1924 +`endif
  1.1925 +`ifdef CFG_MC_DIVIDE_ENABLED
  1.1926 +assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
  1.1927 +assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
  1.1928 +`endif
  1.1929 +assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
  1.1930 +assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
  1.1931 +assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
  1.1932 +`ifdef CFG_DEBUG_ENABLED
  1.1933 +assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
  1.1934 +`endif
  1.1935 +assign load_q_x = (load_x == `TRUE) 
  1.1936 +               && (q_x == `TRUE)
  1.1937 +`ifdef CFG_DEBUG_ENABLED
  1.1938 +               && (bp_match == `FALSE)
  1.1939 +`endif
  1.1940 +                  ;
  1.1941 +assign store_q_x = (store_x == `TRUE) 
  1.1942 +               && (q_x == `TRUE)
  1.1943 +`ifdef CFG_DEBUG_ENABLED
  1.1944 +               && (bp_match == `FALSE)
  1.1945 +`endif
  1.1946 +                  ;
  1.1947 +`ifdef CFG_USER_ENABLED
  1.1948 +assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
  1.1949 +`endif                              
  1.1950 +assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
  1.1951 +assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
  1.1952 +assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
  1.1953 +`ifdef CFG_DEBUG_ENABLED
  1.1954 +assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
  1.1955 +assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));        
  1.1956 +`else
  1.1957 +assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));        
  1.1958 +`endif
  1.1959 +// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
  1.1960 +assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
  1.1961 +assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
  1.1962 +assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
  1.1963 +// The enable that actually does write the registers needs to be qualified with kill
  1.1964 +assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
  1.1965 +
  1.1966 +// Configuration (CFG) CSR
  1.1967 +assign cfg = {
  1.1968 +              `LM32_REVISION,
  1.1969 +              watchpoints[3:0],
  1.1970 +              breakpoints[3:0],
  1.1971 +              interrupts[5:0],
  1.1972 +`ifdef CFG_JTAG_UART_ENABLED
  1.1973 +              `TRUE,
  1.1974 +`else
  1.1975 +              `FALSE,
  1.1976 +`endif
  1.1977 +`ifdef CFG_ROM_DEBUG_ENABLED
  1.1978 +              `TRUE,
  1.1979 +`else
  1.1980 +              `FALSE,
  1.1981 +`endif
  1.1982 +`ifdef CFG_HW_DEBUG_ENABLED
  1.1983 +              `TRUE,
  1.1984 +`else
  1.1985 +              `FALSE,
  1.1986 +`endif
  1.1987 +`ifdef CFG_DEBUG_ENABLED
  1.1988 +              `TRUE,
  1.1989 +`else
  1.1990 +              `FALSE,
  1.1991 +`endif
  1.1992 +`ifdef CFG_ICACHE_ENABLED
  1.1993 +              `TRUE,
  1.1994 +`else
  1.1995 +              `FALSE,
  1.1996 +`endif
  1.1997 +`ifdef CFG_DCACHE_ENABLED
  1.1998 +              `TRUE,
  1.1999 +`else
  1.2000 +              `FALSE,
  1.2001 +`endif
  1.2002 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  1.2003 +              `TRUE,
  1.2004 +`else
  1.2005 +              `FALSE,
  1.2006 +`endif
  1.2007 +`ifdef CFG_USER_ENABLED
  1.2008 +              `TRUE,
  1.2009 +`else
  1.2010 +              `FALSE,
  1.2011 +`endif
  1.2012 +`ifdef CFG_SIGN_EXTEND_ENABLED
  1.2013 +              `TRUE,
  1.2014 +`else
  1.2015 +              `FALSE,
  1.2016 +`endif
  1.2017 +`ifdef LM32_BARREL_SHIFT_ENABLED
  1.2018 +              `TRUE,
  1.2019 +`else
  1.2020 +              `FALSE,
  1.2021 +`endif
  1.2022 +`ifdef CFG_MC_DIVIDE_ENABLED
  1.2023 +              `TRUE,
  1.2024 +`else
  1.2025 +              `FALSE,
  1.2026 +`endif
  1.2027 +`ifdef LM32_MULTIPLY_ENABLED 
  1.2028 +              `TRUE
  1.2029 +`else
  1.2030 +              `FALSE
  1.2031 +`endif
  1.2032 +              };
  1.2033 +
  1.2034 +assign cfg2 = {
  1.2035 +		     30'b0,
  1.2036 +`ifdef CFG_IROM_ENABLED
  1.2037 +		     `TRUE,
  1.2038 +`else
  1.2039 +		     `FALSE,
  1.2040 +`endif
  1.2041 +`ifdef CFG_DRAM_ENABLED
  1.2042 +		     `TRUE
  1.2043 +`else
  1.2044 +		     `FALSE
  1.2045 +`endif
  1.2046 +		     };
  1.2047 +   
  1.2048 +// Cache flush
  1.2049 +`ifdef CFG_ICACHE_ENABLED
  1.2050 +assign iflush =    (csr_write_enable_d == `TRUE) 
  1.2051 +                && (csr_d == `LM32_CSR_ICC)
  1.2052 +                && (stall_d == `FALSE)
  1.2053 +                && (kill_d == `FALSE)
  1.2054 +                && (valid_d == `TRUE);
  1.2055 +`endif 
  1.2056 +`ifdef CFG_DCACHE_ENABLED
  1.2057 +assign dflush_x =  (csr_write_enable_q_x == `TRUE) 
  1.2058 +                && (csr_x == `LM32_CSR_DCC);
  1.2059 +`endif 
  1.2060 +
  1.2061 +// Extract CSR index
  1.2062 +assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
  1.2063 +
  1.2064 +// CSR reads
  1.2065 +always @(*)
  1.2066 +begin
  1.2067 +    case (csr_x)
  1.2068 +`ifdef CFG_INTERRUPTS_ENABLED
  1.2069 +    `LM32_CSR_IE,
  1.2070 +    `LM32_CSR_IM,
  1.2071 +    `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;  
  1.2072 +`endif
  1.2073 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  1.2074 +    `LM32_CSR_CC:   csr_read_data_x = cc;
  1.2075 +`endif
  1.2076 +    `LM32_CSR_CFG:  csr_read_data_x = cfg;
  1.2077 +    `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
  1.2078 +`ifdef CFG_DEBUG_ENABLED
  1.2079 +    `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
  1.2080 +`endif
  1.2081 +`ifdef CFG_JTAG_UART_ENABLED
  1.2082 +    `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;  
  1.2083 +    `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
  1.2084 +`endif
  1.2085 +    `LM32_CSR_CFG2: csr_read_data_x = cfg2;
  1.2086 +      
  1.2087 +    default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
  1.2088 +    endcase
  1.2089 +end
  1.2090 +
  1.2091 +/////////////////////////////////////////////////////
  1.2092 +// Sequential Logic
  1.2093 +/////////////////////////////////////////////////////
  1.2094 +
  1.2095 +// Exception Base Address (EBA) CSR
  1.2096 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2097 +begin
  1.2098 +    if (rst_i == `TRUE)
  1.2099 +        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
  1.2100 +    else
  1.2101 +    begin
  1.2102 +        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
  1.2103 +            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  1.2104 +`ifdef CFG_HW_DEBUG_ENABLED
  1.2105 +        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
  1.2106 +            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  1.2107 +`endif
  1.2108 +    end
  1.2109 +end
  1.2110 +
  1.2111 +`ifdef CFG_DEBUG_ENABLED
  1.2112 +// Debug Exception Base Address (DEBA) CSR
  1.2113 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2114 +begin
  1.2115 +    if (rst_i == `TRUE)
  1.2116 +        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
  1.2117 +    else
  1.2118 +    begin
  1.2119 +        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
  1.2120 +            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  1.2121 +`ifdef CFG_HW_DEBUG_ENABLED
  1.2122 +        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
  1.2123 +            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  1.2124 +`endif
  1.2125 +    end
  1.2126 +end
  1.2127 +`endif
  1.2128 +
  1.2129 +// Cycle Counter (CC) CSR
  1.2130 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  1.2131 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2132 +begin
  1.2133 +    if (rst_i == `TRUE)
  1.2134 +        cc <= {`LM32_WORD_WIDTH{1'b0}};
  1.2135 +    else
  1.2136 +        cc <= cc + 1'b1;
  1.2137 +end
  1.2138 +`endif
  1.2139 +
  1.2140 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.2141 +// Watch for data bus errors
  1.2142 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2143 +begin
  1.2144 +    if (rst_i == `TRUE)
  1.2145 +        data_bus_error_seen <= `FALSE;
  1.2146 +    else
  1.2147 +    begin
  1.2148 +        // Set flag when bus error is detected
  1.2149 +        if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
  1.2150 +            data_bus_error_seen <= `TRUE;
  1.2151 +        // Clear flag when exception is taken
  1.2152 +        if ((exception_m == `TRUE) && (kill_m == `FALSE))
  1.2153 +            data_bus_error_seen <= `FALSE;
  1.2154 +    end
  1.2155 +end
  1.2156 +`endif
  1.2157 + 
  1.2158 +// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
  1.2159 +
  1.2160 +`ifdef CFG_ICACHE_ENABLED
  1.2161 +`ifdef CFG_DCACHE_ENABLED
  1.2162 +always @(*)
  1.2163 +begin
  1.2164 +    if (   (icache_refill_request == `TRUE) 
  1.2165 +        || (dcache_refill_request == `TRUE)
  1.2166 +       )
  1.2167 +        valid_a = `FALSE;
  1.2168 +    else if (   (icache_restart_request == `TRUE) 
  1.2169 +             || (dcache_restart_request == `TRUE) 
  1.2170 +            ) 
  1.2171 +        valid_a = `TRUE;
  1.2172 +    else 
  1.2173 +        valid_a = !icache_refilling && !dcache_refilling;
  1.2174 +end 
  1.2175 +`else
  1.2176 +always @(*)
  1.2177 +begin
  1.2178 +    if (icache_refill_request == `TRUE) 
  1.2179 +        valid_a = `FALSE;
  1.2180 +    else if (icache_restart_request == `TRUE) 
  1.2181 +        valid_a = `TRUE;
  1.2182 +    else 
  1.2183 +        valid_a = !icache_refilling;
  1.2184 +end 
  1.2185 +`endif
  1.2186 +`else
  1.2187 +`ifdef CFG_DCACHE_ENABLED
  1.2188 +always @(*)
  1.2189 +begin
  1.2190 +    if (dcache_refill_request == `TRUE) 
  1.2191 +        valid_a = `FALSE;
  1.2192 +    else if (dcache_restart_request == `TRUE) 
  1.2193 +        valid_a = `TRUE;
  1.2194 +    else 
  1.2195 +        valid_a = !dcache_refilling;
  1.2196 +end 
  1.2197 +`endif
  1.2198 +`endif
  1.2199 +
  1.2200 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2201 +begin
  1.2202 +    if (rst_i == `TRUE)
  1.2203 +    begin
  1.2204 +        valid_f <= `FALSE;
  1.2205 +        valid_d <= `FALSE;
  1.2206 +        valid_x <= `FALSE;
  1.2207 +        valid_m <= `FALSE;
  1.2208 +        valid_w <= `FALSE;
  1.2209 +    end
  1.2210 +    else
  1.2211 +    begin    
  1.2212 +        if ((kill_f == `TRUE) || (stall_a == `FALSE))
  1.2213 +`ifdef LM32_CACHE_ENABLED
  1.2214 +            valid_f <= valid_a;    
  1.2215 +`else
  1.2216 +            valid_f <= `TRUE;
  1.2217 +`endif            
  1.2218 +        else if (stall_f == `FALSE)
  1.2219 +            valid_f <= `FALSE;            
  1.2220 +
  1.2221 +        if (kill_d == `TRUE)
  1.2222 +            valid_d <= `FALSE;
  1.2223 +        else if (stall_f == `FALSE)
  1.2224 +            valid_d <= valid_f & !kill_f;
  1.2225 +        else if (stall_d == `FALSE)
  1.2226 +            valid_d <= `FALSE;
  1.2227 +       
  1.2228 +        if (stall_d == `FALSE)
  1.2229 +            valid_x <= valid_d & !kill_d;
  1.2230 +        else if (kill_x == `TRUE)
  1.2231 +            valid_x <= `FALSE;
  1.2232 +        else if (stall_x == `FALSE)
  1.2233 +            valid_x <= `FALSE;
  1.2234 +
  1.2235 +        if (kill_m == `TRUE)
  1.2236 +            valid_m <= `FALSE;
  1.2237 +        else if (stall_x == `FALSE)
  1.2238 +            valid_m <= valid_x & !kill_x;
  1.2239 +        else if (stall_m == `FALSE)
  1.2240 +            valid_m <= `FALSE;
  1.2241 +
  1.2242 +        if (stall_m == `FALSE)
  1.2243 +            valid_w <= valid_m & !kill_m;
  1.2244 +        else 
  1.2245 +            valid_w <= `FALSE;        
  1.2246 +    end
  1.2247 +end
  1.2248 +
  1.2249 +// Microcode pipeline registers
  1.2250 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2251 +begin
  1.2252 +    if (rst_i == `TRUE)
  1.2253 +    begin
  1.2254 +`ifdef CFG_USER_ENABLED
  1.2255 +        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
  1.2256 +`endif        
  1.2257 +        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
  1.2258 +        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
  1.2259 +        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
  1.2260 +        branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};        
  1.2261 +        x_result_sel_csr_x <= `FALSE;
  1.2262 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  1.2263 +        x_result_sel_mc_arith_x <= `FALSE;
  1.2264 +`endif
  1.2265 +`ifdef LM32_NO_BARREL_SHIFT    
  1.2266 +        x_result_sel_shift_x <= `FALSE;
  1.2267 +`endif
  1.2268 +`ifdef CFG_SIGN_EXTEND_ENABLED
  1.2269 +        x_result_sel_sext_x <= `FALSE;
  1.2270 +`endif    
  1.2271 +        x_result_sel_logic_x <= `FALSE;
  1.2272 +`ifdef CFG_USER_ENABLED
  1.2273 +        x_result_sel_user_x <= `FALSE;
  1.2274 +`endif
  1.2275 +        x_result_sel_add_x <= `FALSE;
  1.2276 +        m_result_sel_compare_x <= `FALSE;
  1.2277 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.2278 +        m_result_sel_shift_x <= `FALSE;
  1.2279 +`endif    
  1.2280 +        w_result_sel_load_x <= `FALSE;
  1.2281 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.2282 +        w_result_sel_mul_x <= `FALSE;
  1.2283 +`endif
  1.2284 +        x_bypass_enable_x <= `FALSE;
  1.2285 +        m_bypass_enable_x <= `FALSE;
  1.2286 +        write_enable_x <= `FALSE;
  1.2287 +        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
  1.2288 +        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
  1.2289 +        load_x <= `FALSE;
  1.2290 +        store_x <= `FALSE;
  1.2291 +        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
  1.2292 +        sign_extend_x <= `FALSE;
  1.2293 +        adder_op_x <= `FALSE;
  1.2294 +        adder_op_x_n <= `FALSE;
  1.2295 +        logic_op_x <= 4'h0;
  1.2296 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.2297 +        direction_x <= `FALSE;
  1.2298 +`endif
  1.2299 +`ifdef CFG_ROTATE_ENABLED
  1.2300 +        rotate_x <= `FALSE;
  1.2301 +
  1.2302 +`endif
  1.2303 +        branch_x <= `FALSE;
  1.2304 +        branch_predict_x <= `FALSE;
  1.2305 +        branch_predict_taken_x <= `FALSE;
  1.2306 +        condition_x <= `LM32_CONDITION_U1;
  1.2307 +`ifdef CFG_DEBUG_ENABLED
  1.2308 +        break_x <= `FALSE;
  1.2309 +`endif
  1.2310 +        scall_x <= `FALSE;
  1.2311 +        eret_x <= `FALSE;
  1.2312 +`ifdef CFG_DEBUG_ENABLED
  1.2313 +        bret_x <= `FALSE;
  1.2314 +`endif
  1.2315 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.2316 +        bus_error_x <= `FALSE;
  1.2317 +        data_bus_error_exception_m <= `FALSE;
  1.2318 +`endif
  1.2319 +        csr_write_enable_x <= `FALSE;
  1.2320 +        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
  1.2321 +        branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
  1.2322 +        m_result_sel_compare_m <= `FALSE;
  1.2323 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.2324 +        m_result_sel_shift_m <= `FALSE;
  1.2325 +`endif    
  1.2326 +        w_result_sel_load_m <= `FALSE;
  1.2327 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.2328 +        w_result_sel_mul_m <= `FALSE;
  1.2329 +`endif
  1.2330 +        m_bypass_enable_m <= `FALSE;
  1.2331 +        branch_m <= `FALSE;
  1.2332 +        branch_predict_m <= `FALSE;
  1.2333 +	branch_predict_taken_m <= `FALSE;
  1.2334 +        exception_m <= `FALSE;
  1.2335 +        load_m <= `FALSE;
  1.2336 +        store_m <= `FALSE;
  1.2337 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.2338 +        direction_m <= `FALSE;
  1.2339 +`endif
  1.2340 +        write_enable_m <= `FALSE;            
  1.2341 +        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
  1.2342 +        condition_met_m <= `FALSE;
  1.2343 +`ifdef CFG_DCACHE_ENABLED
  1.2344 +        dflush_m <= `FALSE;
  1.2345 +`endif
  1.2346 +`ifdef CFG_DEBUG_ENABLED
  1.2347 +        debug_exception_m <= `FALSE;
  1.2348 +        non_debug_exception_m <= `FALSE;        
  1.2349 +`endif
  1.2350 +        operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
  1.2351 +        w_result_sel_load_w <= `FALSE;
  1.2352 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.2353 +        w_result_sel_mul_w <= `FALSE;
  1.2354 +`endif
  1.2355 +        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
  1.2356 +        write_enable_w <= `FALSE;
  1.2357 +`ifdef CFG_DEBUG_ENABLED
  1.2358 +        debug_exception_w <= `FALSE;
  1.2359 +        non_debug_exception_w <= `FALSE;        
  1.2360 +`else
  1.2361 +        exception_w <= `FALSE;
  1.2362 +`endif
  1.2363 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.2364 +        memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
  1.2365 +`endif
  1.2366 +    end
  1.2367 +    else
  1.2368 +    begin
  1.2369 +        // D/X stage registers
  1.2370 +       
  1.2371 +        if (stall_x == `FALSE)
  1.2372 +        begin
  1.2373 +`ifdef CFG_USER_ENABLED
  1.2374 +            user_opcode <= user_opcode_d;       
  1.2375 +`endif        
  1.2376 +            operand_0_x <= d_result_0;
  1.2377 +            operand_1_x <= d_result_1;
  1.2378 +            store_operand_x <= bypass_data_1;
  1.2379 +            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
  1.2380 +            x_result_sel_csr_x <= x_result_sel_csr_d;
  1.2381 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  1.2382 +            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
  1.2383 +`endif
  1.2384 +`ifdef LM32_NO_BARREL_SHIFT    
  1.2385 +            x_result_sel_shift_x <= x_result_sel_shift_d;
  1.2386 +`endif
  1.2387 +`ifdef CFG_SIGN_EXTEND_ENABLED
  1.2388 +            x_result_sel_sext_x <= x_result_sel_sext_d;
  1.2389 +`endif    
  1.2390 +            x_result_sel_logic_x <= x_result_sel_logic_d;
  1.2391 +`ifdef CFG_USER_ENABLED
  1.2392 +            x_result_sel_user_x <= x_result_sel_user_d;
  1.2393 +`endif
  1.2394 +            x_result_sel_add_x <= x_result_sel_add_d;
  1.2395 +            m_result_sel_compare_x <= m_result_sel_compare_d;
  1.2396 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.2397 +            m_result_sel_shift_x <= m_result_sel_shift_d;
  1.2398 +`endif    
  1.2399 +            w_result_sel_load_x <= w_result_sel_load_d;
  1.2400 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.2401 +            w_result_sel_mul_x <= w_result_sel_mul_d;
  1.2402 +`endif
  1.2403 +            x_bypass_enable_x <= x_bypass_enable_d;
  1.2404 +            m_bypass_enable_x <= m_bypass_enable_d;
  1.2405 +            load_x <= load_d;
  1.2406 +            store_x <= store_d;
  1.2407 +            branch_x <= branch_d;
  1.2408 +	    branch_predict_x <= branch_predict_d;
  1.2409 +	    branch_predict_taken_x <= branch_predict_taken_d;
  1.2410 +	    write_idx_x <= write_idx_d;
  1.2411 +            csr_x <= csr_d;
  1.2412 +            size_x <= size_d;
  1.2413 +            sign_extend_x <= sign_extend_d;
  1.2414 +            adder_op_x <= adder_op_d;
  1.2415 +            adder_op_x_n <= ~adder_op_d;
  1.2416 +            logic_op_x <= logic_op_d;
  1.2417 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.2418 +            direction_x <= direction_d;
  1.2419 +`endif
  1.2420 +`ifdef CFG_ROTATE_ENABLED
  1.2421 +            rotate_x <= rotate_d;
  1.2422 +`endif
  1.2423 +            condition_x <= condition_d;
  1.2424 +            csr_write_enable_x <= csr_write_enable_d;
  1.2425 +`ifdef CFG_DEBUG_ENABLED
  1.2426 +            break_x <= break_d;
  1.2427 +`endif
  1.2428 +            scall_x <= scall_d;
  1.2429 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.2430 +            bus_error_x <= bus_error_d;
  1.2431 +`endif
  1.2432 +            eret_x <= eret_d;
  1.2433 +`ifdef CFG_DEBUG_ENABLED
  1.2434 +            bret_x <= bret_d; 
  1.2435 +`endif
  1.2436 +            write_enable_x <= write_enable_d;
  1.2437 +        end
  1.2438 +        
  1.2439 +        // X/M stage registers
  1.2440 +
  1.2441 +        if (stall_m == `FALSE)
  1.2442 +        begin
  1.2443 +            operand_m <= x_result;
  1.2444 +            m_result_sel_compare_m <= m_result_sel_compare_x;
  1.2445 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.2446 +            m_result_sel_shift_m <= m_result_sel_shift_x;
  1.2447 +`endif    
  1.2448 +            if (exception_x == `TRUE)
  1.2449 +            begin
  1.2450 +                w_result_sel_load_m <= `FALSE;
  1.2451 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.2452 +                w_result_sel_mul_m <= `FALSE;
  1.2453 +`endif
  1.2454 +            end
  1.2455 +            else
  1.2456 +            begin
  1.2457 +                w_result_sel_load_m <= w_result_sel_load_x;
  1.2458 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.2459 +                w_result_sel_mul_m <= w_result_sel_mul_x;
  1.2460 +`endif
  1.2461 +            end
  1.2462 +            m_bypass_enable_m <= m_bypass_enable_x;
  1.2463 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1.2464 +            direction_m <= direction_x;
  1.2465 +`endif
  1.2466 +            load_m <= load_x;
  1.2467 +            store_m <= store_x;
  1.2468 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1.2469 +            branch_m <= branch_x && !branch_taken_x;
  1.2470 +`else
  1.2471 +            branch_m <= branch_x;
  1.2472 +	    branch_predict_m <= branch_predict_x;
  1.2473 +	    branch_predict_taken_m <= branch_predict_taken_x;
  1.2474 +`endif
  1.2475 +`ifdef CFG_DEBUG_ENABLED
  1.2476 +	   // Data bus errors are generated by the wishbone and are
  1.2477 +	   // made known to the processor only in next cycle (as a
  1.2478 +	   // non-debug exception). A break instruction can be seen
  1.2479 +	   // in same cycle (causing a debug exception). Handle non
  1.2480 +	   // -debug exception first!
  1.2481 +            if (non_debug_exception_x == `TRUE) 
  1.2482 +                write_idx_m <= `LM32_EA_REG;
  1.2483 +            else if (debug_exception_x == `TRUE)
  1.2484 +                write_idx_m <= `LM32_BA_REG;
  1.2485 +            else 
  1.2486 +                write_idx_m <= write_idx_x;
  1.2487 +`else
  1.2488 +            if (exception_x == `TRUE)
  1.2489 +                write_idx_m <= `LM32_EA_REG;
  1.2490 +            else 
  1.2491 +                write_idx_m <= write_idx_x;
  1.2492 +`endif
  1.2493 +            condition_met_m <= condition_met_x;
  1.2494 +`ifdef CFG_DEBUG_ENABLED
  1.2495 +	   if (exception_x == `TRUE)
  1.2496 +	     if ((dc_re == `TRUE)
  1.2497 +		 || ((debug_exception_x == `TRUE) 
  1.2498 +		     && (non_debug_exception_x == `FALSE)))
  1.2499 +	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
  1.2500 +	     else
  1.2501 +	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
  1.2502 +	   else
  1.2503 +	     branch_target_m <= branch_target_x;
  1.2504 +`else
  1.2505 +            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
  1.2506 +`endif
  1.2507 +`ifdef CFG_TRACE_ENABLED
  1.2508 +            eid_m <= eid_x;
  1.2509 +`endif
  1.2510 +`ifdef CFG_DCACHE_ENABLED
  1.2511 +            dflush_m <= dflush_x;
  1.2512 +`endif
  1.2513 +            eret_m <= eret_q_x;
  1.2514 +`ifdef CFG_DEBUG_ENABLED
  1.2515 +            bret_m <= bret_q_x; 
  1.2516 +`endif
  1.2517 +            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
  1.2518 +`ifdef CFG_DEBUG_ENABLED
  1.2519 +            debug_exception_m <= debug_exception_x;
  1.2520 +            non_debug_exception_m <= non_debug_exception_x;        
  1.2521 +`endif
  1.2522 +        end
  1.2523 +        
  1.2524 +        // State changing regs
  1.2525 +        if (stall_m == `FALSE)
  1.2526 +        begin
  1.2527 +            if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
  1.2528 +                exception_m <= `TRUE;
  1.2529 +            else 
  1.2530 +                exception_m <= `FALSE;
  1.2531 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.2532 +	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
  1.2533 +`ifdef CFG_DEBUG_ENABLED
  1.2534 +					 && (reset_exception == `FALSE)
  1.2535 +`endif
  1.2536 +					 ;
  1.2537 +`endif
  1.2538 +	end
  1.2539 +                
  1.2540 +        // M/W stage registers
  1.2541 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.2542 +        operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
  1.2543 +`else
  1.2544 +        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
  1.2545 +`endif
  1.2546 +        w_result_sel_load_w <= w_result_sel_load_m;
  1.2547 +`ifdef CFG_PL_MULTIPLY_ENABLED
  1.2548 +        w_result_sel_mul_w <= w_result_sel_mul_m;
  1.2549 +`endif
  1.2550 +        write_idx_w <= write_idx_m;
  1.2551 +`ifdef CFG_TRACE_ENABLED
  1.2552 +        eid_w <= eid_m;
  1.2553 +        eret_w <= eret_m;
  1.2554 +`ifdef CFG_DEBUG_ENABLED
  1.2555 +        bret_w <= bret_m; 
  1.2556 +`endif
  1.2557 +`endif
  1.2558 +        write_enable_w <= write_enable_m;
  1.2559 +`ifdef CFG_DEBUG_ENABLED
  1.2560 +        debug_exception_w <= debug_exception_m;
  1.2561 +        non_debug_exception_w <= non_debug_exception_m;
  1.2562 +`else
  1.2563 +        exception_w <= exception_m;
  1.2564 +`endif
  1.2565 +`ifdef CFG_BUS_ERRORS_ENABLED
  1.2566 +        if (   (stall_m == `FALSE)
  1.2567 +            && (   (load_q_m == `TRUE) 
  1.2568 +                || (store_q_m == `TRUE)
  1.2569 +               )
  1.2570 +	   )
  1.2571 +          memop_pc_w <= pc_m;
  1.2572 +`endif
  1.2573 +    end
  1.2574 +end
  1.2575 +
  1.2576 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  1.2577 +// Buffer data read from register file, in case a stall occurs, and watch for
  1.2578 +// any writes to the modified registers
  1.2579 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2580 +begin
  1.2581 +    if (rst_i == `TRUE)
  1.2582 +    begin
  1.2583 +        use_buf <= `FALSE;
  1.2584 +        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
  1.2585 +        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
  1.2586 +    end
  1.2587 +    else
  1.2588 +    begin
  1.2589 +        if (stall_d == `FALSE)
  1.2590 +            use_buf <= `FALSE;
  1.2591 +        else if (use_buf == `FALSE)
  1.2592 +        begin        
  1.2593 +            reg_data_buf_0 <= reg_data_live_0;
  1.2594 +            reg_data_buf_1 <= reg_data_live_1;
  1.2595 +            use_buf <= `TRUE;
  1.2596 +        end        
  1.2597 +        if (reg_write_enable_q_w == `TRUE)
  1.2598 +        begin
  1.2599 +            if (write_idx_w == read_idx_0_d)
  1.2600 +                reg_data_buf_0 <= w_result;
  1.2601 +            if (write_idx_w == read_idx_1_d)
  1.2602 +                reg_data_buf_1 <= w_result;
  1.2603 +        end
  1.2604 +    end
  1.2605 +end
  1.2606 +`endif
  1.2607 +
  1.2608 +`ifdef LM32_EBR_REGISTER_FILE
  1.2609 +`else
  1.2610 +// Register file write port
  1.2611 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2612 +begin
  1.2613 +    if (rst_i == `TRUE) begin
  1.2614 +        registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2615 +        registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2616 +        registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2617 +        registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2618 +        registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2619 +        registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2620 +        registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2621 +        registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2622 +        registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2623 +        registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2624 +        registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2625 +        registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2626 +        registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2627 +        registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2628 +        registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2629 +        registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2630 +        registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2631 +        registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2632 +        registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2633 +        registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2634 +        registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2635 +        registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2636 +        registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2637 +        registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2638 +        registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2639 +        registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2640 +        registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2641 +        registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2642 +        registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2643 +        registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2644 +        registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
  1.2645 +        registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
  1.2646 +        end
  1.2647 +    else begin
  1.2648 +        if (reg_write_enable_q_w == `TRUE)
  1.2649 +          registers[write_idx_w] <= w_result;
  1.2650 +        end
  1.2651 +end
  1.2652 +`endif
  1.2653 +
  1.2654 +`ifdef CFG_TRACE_ENABLED
  1.2655 +// PC tracing logic
  1.2656 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1.2657 +begin
  1.2658 +    if (rst_i == `TRUE)
  1.2659 +    begin
  1.2660 +        trace_pc_valid <= `FALSE;
  1.2661 +        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
  1.2662 +        trace_exception <= `FALSE;
  1.2663 +        trace_eid <= `LM32_EID_RESET;
  1.2664 +        trace_eret <= `FALSE;
  1.2665 +`ifdef CFG_DEBUG_ENABLED
  1.2666 +        trace_bret <= `FALSE;
  1.2667 +`endif
  1.2668 +        pc_c <= `CFG_EBA_RESET/4;
  1.2669 +    end
  1.2670 +    else
  1.2671 +    begin
  1.2672 +        trace_pc_valid <= `FALSE;
  1.2673 +        // Has an exception occured
  1.2674 +`ifdef CFG_DEBUG_ENABLED
  1.2675 +        if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
  1.2676 +`else
  1.2677 +        if (exception_q_w == `TRUE)
  1.2678 +`endif
  1.2679 +        begin        
  1.2680 +            trace_exception <= `TRUE;
  1.2681 +            trace_pc_valid <= `TRUE;
  1.2682 +            trace_pc <= pc_w;
  1.2683 +            trace_eid <= eid_w;
  1.2684 +        end
  1.2685 +        else
  1.2686 +            trace_exception <= `FALSE;
  1.2687 +        
  1.2688 +        if ((valid_w == `TRUE) && (!kill_w))
  1.2689 +        begin
  1.2690 +            // An instruction is commiting. Determine if it is non-sequential
  1.2691 +            if (pc_c + 1'b1 != pc_w)
  1.2692 +            begin
  1.2693 +                // Non-sequential instruction
  1.2694 +                trace_pc_valid <= `TRUE;
  1.2695 +                trace_pc <= pc_w;
  1.2696 +            end
  1.2697 +            // Record PC so we can determine if next instruction is sequential or not
  1.2698 +            pc_c <= pc_w;
  1.2699 +            // Indicate if it was an eret/bret instruction
  1.2700 +            trace_eret <= eret_w;
  1.2701 +`ifdef CFG_DEBUG_ENABLED
  1.2702 +            trace_bret <= bret_w;
  1.2703 +`endif
  1.2704 +        end
  1.2705 +        else
  1.2706 +        begin
  1.2707 +            trace_eret <= `FALSE;
  1.2708 +`ifdef CFG_DEBUG_ENABLED
  1.2709 +            trace_bret <= `FALSE;
  1.2710 +`endif
  1.2711 +        end
  1.2712 +    end
  1.2713 +end
  1.2714 +`endif
  1.2715 +      
  1.2716 +/////////////////////////////////////////////////////
  1.2717 +// Behavioural Logic
  1.2718 +/////////////////////////////////////////////////////
  1.2719 +
  1.2720 +// synthesis translate_off            
  1.2721 +
  1.2722 +// Reset register 0. Only needed for simulation. 
  1.2723 +initial
  1.2724 +begin
  1.2725 +`ifdef LM32_EBR_REGISTER_FILE
  1.2726 +    reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  1.2727 +    reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  1.2728 +`else
  1.2729 +    registers[0] = {`LM32_WORD_WIDTH{1'b0}};
  1.2730 +`endif
  1.2731 +end
  1.2732 +
  1.2733 +// synthesis translate_on
  1.2734 +        
  1.2735 +endmodule